IP Library Granted Patent US 7,413,953
Granted Patent B2
US 7,413,953 · App. 11/641,034 · Granted Aug 19, 2008

Method of forming floating gate array of flash memory device

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Quick Facts
Patent No.
US 7,413,953
App. No.
11/641,034
Filed
Dec 19, 2006
Granted
Aug 19, 2008
Kind
B2
Art Unit
2823
USPC
438/257
Abstract

The method of forming a floating gate array of a flash memory device includes: (a) sequentially forming a tunnel oxide film, a floating gate forming film, a capping oxide film and a first nitride film on a semiconductor substrate with an active device region defined by device isolation films; (b) patterning the first nitride film to form a first nitride film pattern; (c) forming first oxide film spacers on sidewalls of the first nitride film pattern; (d) selectively removing the first nitride film pattern; (e) forming a plurality of second nitride film patterns separated by the first oxide film spacers on the capping oxide film; (f) selectively removing the first oxide film spacers interposed between the plurality of second nitride film patterns and a portion of the capping oxide film to expose a surface of the floating gate forming film between the second nitride film patterns; (g) forming a plurality of floating gate patterns by removing a portion of the floating gate forming film exposed using the second nitride film patterns as an etching mask; and (h) oxidizing the sidewall of each of the plurality of floating gate patterns to form sidewall oxide films therebetween.

Claims (18)

1. A method of forming a floating gate array of a flash memory device, comprising the:

(a) sequentially forming a tunnel oxide film, a floating gate forming film, a capping oxide film and a first nitride film on a semiconductor substrate with an active device region defined by device isolation films;

(b) patterning the first nitride film to form a first nitride film pattern;

(c) forming first oxide film spacers on sidewalls of the first nitride film pattern;

(d) selectively removing the first nitride film pattern;

(e) forming a plurality of second nitride film patterns separated by the first oxide film spacers on the capping oxide film;

(f) selectively removing the first oxide film spacers interposed between the plurality of second nitride film patterns and a portion of the capping oxide film to expose a surface of the floating gate forming film between the second nitride film patterns;

(g) forming a plurality of floating gate patterns by removing a portion of the floating gate forming film exposed using the second nitride film patterns as an etching mask; and

(h) oxidizing the sidewall of each of the plurality of floating gate patterns to form sidewall oxide films therebetween; and

wherein step (e) further comprises:

forming a second nitride film on the capping oxide film; and

planarizing a top of the second nitride film until tops of the first oxide film spacers are exposed.

2. The method of claim 1 , comprising: forming the floating gate forming film of a polycrystalline silicon film.

3. The method of claim 2 , wherein the first nitride film pattern formed in the step (b) is formed on only one active device region among active device regions of two neighboring memory cells.

4. The method of claim 2 , wherein the step (f) is performed using a wet etching process in which the first oxide film spacers and the capping oxide film can be selectively removed.

5. The method of claim 2 , wherein the step (h) is performed using a thermal oxidation process.

6. The method of claim 2 , further comprising removing the second nitride film patterns on tops of a plurality of floating gate patterns after the step (h).

7. The method of claim 6 , wherein removing the second nitride film patterns is performed using a wet etching process.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041374/0793 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2006
From: CHOI, JONG WOON
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018723/0676 →