Semiconductor integrated circuit and data processing system
View Patent ↗To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
1. A semiconductor device comprising:
a memory cell array having a plurality of word lines, a plurality of bit lines across the plurality of word lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit lines;
a plurality of sense amplifiers connected to the plurality of bit lines; and
a plurality of column switches connected to the plurality of bit lines,
wherein in a first mode, all memory cells connected to a first word line included in the plurality of word lines are written with data during activation of the first word line,
wherein in a second mode, a predetermined number of memory cells connected to the first word line are written with data during activation of the first word line,
wherein a time from activating the first word line to activating the column switches in the first mode is shorter than that in the second mode.
2. A semiconductor device according to claim 1 ,
wherein each of the plurality of column switches is controlled by corresponding one of a plurality of column selection signals,
wherein all of the plurality of column selection signals are activated sequentially during activation the first word line.
3. A semiconductor device according to claim 1 , further comprising:
a plurality of global bit lines connected to the plurality of column switches;
a plurality of main amplifiers connected to the plurality of global bit lines,
wherein the data written into the plurality of memory cells are outputted from the plurality of main amplifiers.
4. A semiconductor device according to claim 1 ,
wherein the plurality of memory cells are DRAM cells.
5. A semiconductor device according to claim 4 ,
wherein the semiconductor device is used for a second level cache.
6. A semiconductor device according to claim 1 ,
wherein the plurality of column switches are selected after the first word line is selected without waiting for activation of the plurality of sense amplifiers.
7. A semiconductor device according to claim 1 ,
wherein the plurality of column switches are selected at the same timing of rising of the first word line.