IP Library Granted Patent US 7,793,414
Granted Patent B2
US 7,793,414 · App. 11/642,570 · Granted Sep 14, 2010

Methods for forming connection structures for microelectronic devices

Assignee: Tessera, Inc.
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Quick Facts
Patent No.
US 7,793,414
App. No.
11/642,570
Granted
Sep 14, 2010
Kind
B2
Abstract

Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Claims (43)

1. A method for forming a connection structure for a microelectronic device, comprising:

(a) providing a first layer, wherein said first layer is comprised of a substrate having first and second opposing surfaces, a plurality of holes extending through the first and second surfaces, and a plurality of first posts, each post being electrically conductive and extending from a base at the first surface of the first substrate toward a tip; and

(b) then positioning a plurality of second posts, wherein each post is electrically conductive and extends from a base toward a tip in a corresponding hole of the substrate,

with a dielectric material between the substrate and at least one of the second posts, the dielectric material providing adhesion between the substrate and surfaces of the plurality of second posts between the first and second opposing surfaces of the first substrate.

2. The method of claim 1 , wherein step (a) comprises forming the first posts for the first layer by a subtractive process.

3. The method of claim 1 , wherein step (a) comprises forming the first posts by an additive process.

4. The method of claim 1 , wherein step (a) comprises forming the first posts by a mechanical process.

5. The method of claim 4 , wherein step (a) comprises stamping a sheet of electrically conductive material.

6. The method of claim 1 , wherein step (a) comprises etching the substrate of the first layer to form the holes therein.

7. The method of claim 6 , wherein step (a) comprises using the same etchant to form both the holes and the posts of the first layer.

8. The method of claim 1 , wherein step (a) comprises cutting the substrate of the first layer to form the plurality of holes therein.

9. The method of claim 8 , wherein the substrate is cut using a punch.

10. The method of claim 1 , wherein the dielectric material is a polymeric material.

11. The method of claim 10 , wherein step (b) further comprises subjecting the polymeric material to conditions effective to bond the substrates, thereby forming a laminate structure.

12. The method of claim 11 , wherein step (b) further comprises heating the polymeric material.

13. The method of claim 1 , further comprising (c) electrically isolating a selected post from the plurality of first posts of the first layer from the other posts of the first layer.

14. The method of claim 13 , further comprising (c) comprises cutting the substrate into discontiguous sections.

15. A method for forming a connection structure for a microelectronic device, comprising:

(a) providing

a first layer, comprising a substrate having a first surface, a second surface opposing the first surfaces, and a plurality of holes extending through the first and second surfaces, and a plurality of first electrically conductive posts, each first post extending from a base at the first surface toward a tip, and

a second layer comprising a plurality of second posts, each second post being electrically conductive and extending from a base toward a tip; and

(b) then positioning the second layer such that the second posts extend through a dielectric material and each tip of the second posts is located in a corresponding hole of the first substrate,

the dielectric material providing adhesion between the substrate and surfaces of the second posts between the first and second surfaces of the first substrate.

16. A method for forming a connection structure for a microelectronic device, comprising:

(a) providing

a first layer, comprising a first substrate having first and second opposing surfaces and a plurality of holes extending through the first and second surfaces, and

a second layer, comprising a second substrate and a plurality of posts, each post being electrically conductive and extending from a base at a surface of the second substrate toward a tip; and

(b) then positioning the layers such that the surface of the second substrate faces the first surface of the substrate, each tip of the posts is located within a corresponding hole of the first substrate, and a dielectric material is interposed between the substrates,

the dielectric material providing adhesion between the first substrate and surfaces of the plurality of posts between the first and second opposing surfaces of the first substrate.

17. A method for forming a connection structure for a microelectronic device, comprising:

(a) providing

a first substrate having first and second opposing surfaces and a plurality of holes extending through the first and second surfaces,

a second substrate having a surface facing the first surface of the first substrate, and a plurality of posts, each post being electrically conductive and extending from a base at the surface of the second substrate toward a tip; and

(b) then positioning the second substrate such that the posts extend through a dielectric material and each tip of the posts is located in a corresponding hole of the first substrate,

the dielectric material providing adhesion between the first substrate and surfaces of the plurality of posts between the first and second surfaces of the first substrate.

18. A method for forming a connection structure for a microelectronic device, comprising:

(a) providing a first layer, wherein said first layer is comprised of a substrate having first and second opposing surfaces, a plurality of holes extending through the first and second surfaces, and a plurality of first posts, each post being electrically conductive and extending from a base at the first surface of the first substrate toward a tip, the first posts being formed by selectively removing material from an electrically conductive sheet on the first surface of the substrate of the first layer; and

(b) positioning a plurality of second posts, wherein each of the second posts post is electrically conductive and extends from a base toward a tip in a corresponding hole of the substrate,

with a dielectric material providing adhesion between the substrate and at least one of the second posts.

19. The method of claim 18 , wherein material is selectively removed by etching the conductive layer.

20. The method of claim 18 , wherein step (a) comprises selectively removing material from a unitary sheet of electrically conductive material, thereby forming the first posts as an integral part of the substrate for the first layer.

21. The method of claim 18 , wherein material is selectively removed by etching the conductive layer.

22. The method of claim 18 , wherein step (a) comprises selectively removing material from a unitary sheet of electrically conductive material, thereby forming the first posts as an integral part of the substrate for the first layer.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0661 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2010
From: HABA, BELGACEM; BEROZ, MASUD; TUCKERMAN, DAVID B.; HUMPSTON, GILES; CRISP, RICHARD DEWITT
To: TESSERA, INC.
Reel/Frame 024556/0429 →
Continuity (2)
Division 1091797800 · Aug 13, 2004
Related Publication 20070094874A1 · May 3, 2007