Patent Assignment
Reel/Frame 073658/0661
Change of Name
Recorded: 2025-11-21
Pages: 7
Assignor
TESSERA LLC
Executed: 2022-08-15
Assignee
ADEIA SEMICONDUCTOR SOLUTIONS LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(100)
Method of Making a Connection Component with Posts and Pads
Microelectronic Package Comprising Offset Conductive Posts on Compliant Layer
Compact Lens Turret Assembly
High Q Cavity Resonators for Microelectronics
Image Sensor Package and Fabrication Method
Microelectronic Package Having Stacked Semiconductor Devices and a Process for Its Fabrication
Stacked Microelectronic Packages Having at Least Two Stacked Microelectronic Elements Adjacent One Another
Stacked Microelectronic Packages Having at Least Two Stacked Microelectronic Elements Adjacent One Another
Methods for Forming Connection Structures for Microelectronic Devices
Stacked Packaging Improvements
Stacked Packaging Improvements
Stacked Packaging Improvements
Multi-Sheet Conductive Substrates for Microelectronic Devices and Methods for Forming Such Substrates
Microelectronic Elements with Compliant Terminal Mountings and Methods for Making the Same
Stack Microelectronic Assemblies
Microelectronic Packages and Methods Therefor
Microelectronic Component with Foam-Metal Posts
Microelectronic Connection Component
Small Chips with Fan-Out Leads
Packaged Chip Having Features for Improved Signal Transmission on the Package
Microelectronic Packages Fabricated at the Wafer Level and Methods Therefor
Microelectronic Packages Fabricated at the Wafer Level and Methods Therefor
Microelectronic Packages and Methods Therefor
Microelectronic Packages and Methods Therefor
Microelectronic Packages and Methods Therefor
Microelectronic Packages and Methods Therefor
Method for Making a Microelectronic Assembly Having Conductive Elements
Microelectronic Package Having Interconnected Redistribution Paths
Image Sensor Employing a Plurality of Photodetector Arrays and/or Rear-Illuminated Architecture
Compliant Terminal Mountings with Vented Spaces and Methods
Microelectronic Component with Photo-Imageable Substrate
Pin Referenced Image Sensor to Reduce Tilt in a Camera Module
Microelectronic Assemblies Having Very Fine Pitch Stacking
Microelectronic Package with Thermal Access
Microelectronic Package with Thermal Access
Substrate for a Microelectronic Package and Method of Fabricating Thereof
Microelectronic Package Element and Method of Fabricating Thereof
Substrate for a Microelectronic Package and Method of Fabricating Thereof
Substrate for a Microelectronic Package and Method of Fabricating Thereof
Low Loss Rf Transmission Lines Having a Reference Conductor with a Recess Portion Opposite a Signal Conductor
Stackable Microelectronic Device Carriers, Stacked Device Carriers and Methods of Making the Same
Substrate for a Flexible Microelectronic Assembly and a Method of Fabricating Thereof
Ultra-Thin Near-Hermetic Package Based on Rainier
Wafer Level Chip Package and a Method of Fabricating Thereof
Wafer Level Chip Package and a Method of Fabricating Thereof
Collective and Synergistic Mram Shields
Layered Metal Structure for Interconnect Element
Enabling Uniformity of Stacking Process Through Bumpers
Edge Connect Wafer Level Stacking
Edge Connect Wafer Level Stacking
Edge Connect Wafer Level Stacking
Method of Making a Stacked Microelectronic Package
Method of making a stacked microelectronic package
Stacked packages with bridging traces
Method of Fabricating Stacked Packages with Bridging Traces
Microelectronic Packages Having Cavities for Receiving Microelectric Elements
Microelectronic Packages Having Cavities for Receiving Microelectronic Elements
Microelectronic Packages Having Cavities for Receiving Microelectronic Elements
Packaged Semiconductor Chips
Packaged Semiconductor Chips
Packaged Semiconductor Chips with Array
Packaged Semiconductor Chips with Array
Packaged Semiconductor Chips with Array
Packaged Semiconductor Chips with Array
Chip Assembly Including Package Element and Integrated Circuit Chip
Microelectronic Assemblies Having Compliancy and Methods Therefor
Microelectronic Assemblies Having Compliancy and Methods Therefor
Microelectronic Assemblies Having Compliancy and Methods Therefor
Multilayer Wiring Element Having Pin Interface
Wearable Ultra-Thin Miniaturized Mobile Communications
Wearable Ultra-Thin Miniaturized Mobile Communications
Method of Fabricating Stacked Assembly Including Plurality of Stacked Microelectronic Elements
Reconstituted Wafer Level Stacking
Off-Chip Vias in Stacked Chips
Off-Chip Vias in Stacked Chips
Reconstituted Wafer Stack Packaging with After-Applied Pad Extensions
A Method of Fabricating an Interconnection Element Having Conductive Posts
Interconnection Element with Posts Formed by Plating
Flip Chip Interconnection with Double Post
Robust Multi-Layer Wiring Elements and Assemblies with Embedded Microelectronic Elements
Microelectronic Assembly with Impedance Controlled Wirebond and Conductive Reference Element
Microelectronic Assembly with Impedance Controlled Wirebond and Reference Wirebond
Microelectronic Assembly with Impedance Controlled Wirebond and Conductive Reference Element
Microelectronic Assembly with Impedance Controlled Wirebond and Conductive Reference Element
Microelectronic Assembly with Impedance Controlled Wirebond and Reference Wirebond
Wafer Level Edge Stacking
Tsop with Impedance Control
Stackable Molded Microelectronic Packages
Stackable Molded Microelectronic Packages
Stackable Molded Microelectronic Packages
Stackable Molded Microelectronic Packages
Stackable Molded Microelectronic Packages
Microelectronic Packages with Dual or Multiple-Etched Flip-Chip Connectors
Microelectronic Packages with Dual or Multiple-Etched Flip-Chip Connectors
Microelectronic Packages with Nanoparticle Joining
Microelectronic Packages with Nanoparticle Joining
Microelectronic Elements Having Metallic Pads Overlying Vias
Microelectronic Elements with Rear Contacts Connected with via First or via Middle Structures
Methods of Forming Semiconductor Elements Using Micro-Abrasive Particle Stream
Non-Lithographic Formation of Three-Dimensional Conductive Elements
Related Assignments
(21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 4, 2005
From: CRISP, RICHARD DEWITT; HABA, BELGACEM; HUMPSTON, GILES
To: TESSERA, INC.
Reel/Frame 016005/0685 →
Assignment of Assignor's Interest
Apr 25, 2005
From: HABA, BELGACEM; BEROZ, MASUD; HUMPSTON, GILES; PARK, JAE M.
To: TESSERA, INC.
Reel/Frame 016150/0261 →
Assignment of Assignor's Interest
Apr 25, 2005
From: BEROZ, MASUD; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 016150/0191 →
Assignment of Assignor's Interest
Jun 27, 2005
From: HUMPSTON, GILES
To: TESSERA, INC.
Reel/Frame 016425/0927 →
Assignment of Assignor's Interest
Aug 30, 2005
From: KANG, TECK-GYU; ESTRELLA, MICHAEL; PARK, JAE M.; THOMPSON, KENNETH ROBERT
To: TESSERA, INC.
Reel/Frame 016683/0829 →
Assignment of Assignor's Interest
Feb 6, 2006
From: GREEN, RONALD
To: TESSERA, INC.
Reel/Frame 017238/0622 →
Assignment of Assignor's Interest
Feb 10, 2006
From: MOHAMMED, ILYAS; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 017278/0182 →
Assignment of Assignor's Interest
Jun 21, 2006
From: HABA, BELGACEM; MOHAMMED, ILYAS; MITCHELL, CRAIG S.; WARNER, MICHAEL
To: TESSERA, INC.
Reel/Frame 017832/0647 →
Assignment of Assignor's Interest
Jan 17, 2007
From: WILSON, STUART E.; GREEN, RONALD; CRISP, RICHARD DEWITT; HUMPSTON, GILES
To: TESSERA, INC.
Reel/Frame 018784/0278 →
Assignment of Assignor's Interest
Feb 8, 2007
From: HUMPSTON, GILES; THOMPSON, JESSE BURL
To: TESSERA, INC.
Reel/Frame 018880/0539 →
Assignment of Assignor's Interest
Feb 12, 2007
From: HUMPSTON, GILES; GAO, GUILIAN; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 018892/0969 →
Assignment of Assignor's Interest
Jul 15, 2009
From: KUBOTA, YOICHI; KANG, TECK-GYU; PARK, JAE M.; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 022972/0592 →
Assignment of Assignor's Interest
Jun 17, 2010
From: HABA, BELGACEM; BEROZ, MASUD; TUCKERMAN, DAVID B.; HUMPSTON, GILES
To: TESSERA, INC.
Reel/Frame 024556/0429 →
Assignment of Assignor's Interest
Sep 9, 2013
From: HABA, BELGACEM; MITCHELL, CRAIG S.; BEROZ, MASUD
To: TESSERA, INC.
Reel/Frame 031262/0655 →
Assignment of Assignor's Interest
Aug 18, 2015
From: HABA, BELGACEM; MITCHELL, CRAIG S.; BEROZ, MASUD
To: TESSERA, INC.
Reel/Frame 036344/0951 →
Assignment of Assignor's Interest
Oct 2, 2015
From: HABA, BELGACEM; MITCHELL, CRAIG S.; BEROZ, MASUD
To: TESSERA, INC.
Reel/Frame 036716/0704 →
Assignment of Assignor's Interest
Jan 14, 2016
From: MOHAMMED, ILYAS; HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 037489/0613 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →