Method of fabricating stacked assembly including plurality of stacked microelectronic elements

1. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:

a) providing first and second microelectronic substrates each including a plurality of microelectronic elements attached together at dicing lanes, each of said plurality of microelectronic elements including a first edge and a second edge remote from said first edge, each of said plurality of microelectronic elements further including contacts and traces extending from said contacts to identical locations proximate said first and second edges;

b) stacking and joining said first and second microelectronic substrates in first and second different orientations to form a stacked assembly such that said first edges of said microelectronic elements of said first microelectronic substrate are aligned with said second edges of said microelectronic elements of said second microelectronic substrate;

c) exposing said traces at said first and second edges of said microelectronic elements of said first and second microelectronic substrates, respectively; and

d) forming first and second leads, said first leads connected to said exposed traces of said microelectronic elements of said first microelectronic substrate, said second leads connected to said exposed traces of said microelectronic elements of said second microelectronic substrate, said second leads being electrically isolated from said first leads.

2. A method of fabricating a stacked assembly as claimed in claim 1 , wherein said first and second leads extend in parallel paths along said first edges of said microelectronic elements of said first microelectronic substrate.

3. A method as claimed in claim 2 , further comprising severing said stacked assembly along said first and second edges into a plurality of unit assemblies each including at least one of said microelectronic elements of said first microelectronic substrate and at least one of said microelectronic elements of said second microelectronic substrate.

4. A method of fabricating a stacked assembly as claimed in claim 1 , wherein each of said microelectronic elements has north-south edges and east-west edges, wherein said traces extend from contacts adjacent to said north-south edges towards said east-west edges.

5. A method of fabricating a stacked assembly as claimed in claim 1 , wherein each of said microelectronic elements has north-south edges and east-west edges, said east-west edges including said first and second edges, wherein said traces extend from contacts adjacent to said north-south edges towards said east-west edges.

6. A method of fabricating a stacked assembly as claimed in claim 1 , wherein said first and second leads extend in parallel paths along at least said first and second edges of said plurality of edges.

7. A method of fabricating a stacked assembly as claimed in claim 1 , wherein first faces of said microelectronic elements of said first and second microelectronic substrates confront each other.

8. A method of fabricating a stacked assembly as claimed in claim 1 , further comprising aligning and joining a third microelectronic substrate with said first and second microelectronic substrates, said third microelectronic substrate having a third orientation different from said first and second orientations, wherein third traces extending along first faces of third microelectronic elements of said third microelectronic substrate extend in interleaved paths with said first and second traces of said microelectronic elements of said first and second microelectronic substrates, and said stacked assembly further includes third leads connected to said third traces, respectively, said third leads extending along said first and second edges and being interleaved with and electrically isolated from said first and second leads.

9. A method of fabricating a stacked assembly as claimed in claim 8 , further comprising aligning and joining a fourth microelectronic substrate with said first, second and third microelectronic substrates, said fourth microelectronic substrate having a fourth orientation different from said first, second and third orientations, wherein fourth traces extending along first faces of microelectronic elements of said fourth microelectronic substrate extend in interleaved paths with said first, second and third traces, and said stacked assembly further includes fourth leads connected to said fourth traces, said fourth leads extending along said first and second edges and being interleaved with and electrically isolated from said first, second and third leads.

10. A method of fabricating a stacked assembly as claimed in claim 9 , wherein first faces of said microelectronic elements of said first and second microelectronic substrates and said first faces of said microelectronic elements of said third and fourth microelectronic substrates each have the same width and each have the same length.

11. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:

a) providing a plurality of microelectronic substrates, each said microelectronic substrate including a plurality of like microelectronic elements each having a face and first and second edges extending away from said face, each of said microelectronic elements having contacts at said face and traces extending along said face from said contacts to locations proximate said first and second edges, said traces of each said microelectronic element extending in a lengthwise direction and being spaced apart in a lateral direction, transverse to said lengthwise direction;

b) stacking and joining said plurality of microelectronic substrates in different orientations such that said first edges of said microelectronic elements of a first one of said microelectronic substrates are aligned with corresponding second edges of said microelectronic elements of each other of said plurality of stacked and joined microelectronic substrates and each of said traces of said microelectronic elements of said first microelectronic substrate at said first edges is spaced laterally from each of said traces of said microelectronic elements of any other of said stacked and joined microelectronic substrates.

12. A method of fabricating a stacked assembly as claimed in claim 11 , further comprising:

c) exposing said traces at said first and second edges of said microelectronic elements of said plurality of stacked, joined microelectronic substrates; and

d) forming leads, said leads connected to said exposed traces of said microelectronic elements of said stacked, joined microelectronic substrates.

13. A method of fabricating a stacked assembly as claimed in claim 12 , wherein said leads extend in parallel paths along said first edges of said microelectronic elements.

14. A method of fabricating a stacked assembly as claimed in claim 12 , wherein step (b) includes stacking and joining first, second and third substrates having first, second and third different orientations and step (d) includes forming first leads connected to first traces of said microelectronic elements of said first microelectronic substrate, second leads connected to second traces of said microelectronic elements of said second microelectronic substrate, and third leads connected to third traces of said microelectronic elements of said third microelectronic substrate, respectively, wherein at least some of said leads of each of said first, second and third microelectronic substrates are electrically isolated from said leads of any other of said first, second and third microelectronic substrates.

15. A method of fabricating a stacked assembly as claimed in claim 12 , wherein step (b) includes stacking and joining first, second, third and fourth substrates having first, second, third and fourth different orientations and step (d) includes forming first leads connected to first traces of said microelectronic elements of said first microelectronic substrate, second leads connected to second traces of said microelectronic elements of said second microelectronic substrate, third leads connected to third traces of said microelectronic elements of said third microelectronic substrate, and fourth leads connected to fourth traces of said microelectronic elements of said fourth microelectronic substrate, wherein at least some of said leads of each of said first, second, third and fourth microelectronic substrates are electrically isolated from said leads of any other of said first, second, third and fourth microelectronic substrates.

16. A method of fabricating a stacked assembly including a plurality of stacked microelectronic elements, comprising:

a) providing a plurality of microelectronic substrates, each of said microelectronic substrates including a plurality of microelectronic elements attached together at edges defined by dicing lanes, said edges including first and second edges, each of said microelectronic elements having a face extending between said first and second edges, each said microelectronic substrate having bond pads at said face and redistribution traces extending along said face from said bond pads towards said first and second edges, said redistribution traces of each said microelectronic substrate having a pitch, said pitch being greater than a number N multiplied by a width of said redistribution traces at said first edge, N being greater than two, said redistribution traces at said first edge being offset from said redistribution traces at said second edge in a direction of said pitch of said redistribution traces;

b) stacking a second one of said microelectronic substrates in a first orientation onto a first one of said microelectronic substrates in a second orientation such that said redistribution traces at said first edge of each microelectronic element of said first microelectronic substrate are offset from said redistribution traces of each corresponding microelectronic element of said second microelectronic substrate directly overlying said microelectronic element of said first microelectronic substrate;

c) forming leads connected to said redistribution traces, said leads extending about said first and second edges of said microelectronic elements of said first and second microelectronic substrates; and

d) dicing said stacked first and second microelectronic substrates along said dicing lanes into individual stacked assemblies having first and second edges, wherein closest adjacent leads at said first edges are laterally spaced from each other.