IP Library Granted Patent US 7,952,195
Granted Patent B2
US 7,952,195 · App. 11/648,172 · Granted May 31, 2011

Stacked packages with bridging traces

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Quick Facts
Patent No.
US 7,952,195
App. No.
11/648,172
Granted
May 31, 2011
Kind
B2
Abstract

A microelectronic assembly that includes a first microelectronic element having a first rear surface. The assembly further includes a second microelectronic element having a second rear surface. The second microelectronic element is attached to the first microelectronic element so as to form a stacked package. A bridging element electrically connects the first microelectronic element and the second microelectronic element. The first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.

Claims (20)

1. A microelectronic assembly comprising:

a first microelectronic element having a front surface, first contacts exposed at the front surface, a rear surface opposite the front surface, and a first edge surface extending between the front and rear surfaces;

a second microelectronic element having a front surface, second contacts exposed at such front surface, a rear surface opposite such front surface, and a second edge surface extending between the front and rear surfaces, the first and second microelectronic elements attached to one another with the rear surfaces of the first and second microelectronic elements facing one another;

a layer extending between the rear surfaces of the first and second microelectronic elements;

at least one bridging element extending between at least one of the first contacts and at least one of the second contacts so as to electrically connect the two, wherein the at least one first contact and the at least one second contact remain exposed for electrically connecting the microelectronic assembly to a substrate external to the microelectronic assembly,

the at least one bridging element extending as a continuous trace along the first and second edge surfaces and along a surface of the layer between the rear surfaces of the first and second microelectronic elements, wherein the layer provides electrical isolation between the at least one bridging element and the bodies of the microelectronic elements.

2. The microelectronic assembly of claim 1 , further comprising a plurality of traces exposed on the respective front surfaces of the first microelectronic element and second microelectronic element, at least some of the plurality of traces extending from at least some of the first contacts to the at least one bridging element and at least some of the plurality of traces extending from at least some of the second contacts to the at least one bridging element.

3. The microelectronic assembly of claim 2 , wherein the layer includes an adhesive bonding the rear surfaces of the first and second microelectronic elements to one another.

4. The microelectronic assembly of claim 1 , further comprising a third microelectronic element having a front face and a rear face, and

a fourth microelectronic element having a rear face,

wherein the third and fourth microelectronic elements are attached such that the rear face of the third microelectronic element faces toward the rear face of the fourth microelectronic element,

the third microelectronic element also being attached to the first and second microelectronic elements such that the front face of the third microelectronic element faces toward the front surface of the second microelectronic element.

5. The microelectronic assembly of claim 1 , further comprising masses of conductive material disposed on the plurality of contacts, the conductive material masses enabling electrical connection to the substrate.

6. The microelectronic assembly of claim 1 , wherein the bridging elements further include traces extending from the plurality of contacts along the front surfaces of the first and second microelectronic elements.

7. The microelectronic assembly of claim 1 , wherein the surface of the layer is arranged in at least substantial alignment with the first and second edge surfaces.

8. A microelectronic assembly comprising:

a first microelectronic element having a front surface, first contacts exposed at the front surface, a rear surface opposite the front surface, and a first edge surface extending between the front and rear surfaces;

a second microelectronic element having a front surface, second contacts exposed at such front surface, a rear surface opposite such front surface, and a second edge surface extending between the front and rear surfaces, the first and second microelectronic elements attached to one another with the rear surfaces of the first and second microelectronic elements facing one another;

an adhesive layer bonding the rear surfaces of the first and second microelectronic elements and having an edge surface arranged in at least substantial alignment with the edge surfaces of the first and second microelectronic elements;

at least one bridging element extending between at least one of the first contacts and at least one of the second contacts so as to electrically connect the two, wherein the at least one first contact and the at least one second contact remain exposed for electrically connecting the microelectronic assembly to a substrate external to the microelectronic assembly, the at least one bridging element extending as a continuous trace along the first and second edge surfaces and along a surface of the adhesive layer between the rear surfaces of the first and second microelectronic elements.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0661 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2007
From: HABA, BELGACEM
To: TESSERA, INC.
Reel/Frame 019752/0858 →