Packaged semiconductor chips

1. A chip-sized wafer level packaged device comprising:

a chip embodying a device, said chip having a surface, an opposed surface, and bond pads at said surface;

a chip-sized silicon packaging layer overlying an opposed surface of said chip, said packaging layer comprising a material having thermal expansion characteristics similar to those of said semiconductor wafer, the silicon packaging layer having a surface facing away from said chip, and openings extending through said packaging layer at locations overlying said bond pads, the chip and the packaging layer having edge surfaces extending away from the surface of the chip and the surface of the packaging layer, respectively;

a ball grid array formed over said surface of said packaging layer and being electrically coupled to said bond pads;

an insulating layer coating inner surfaces of at least some of the openings;

a compliant layer including platforms formed of compliant material different from a material of the insulating layer overlying said surface of said packaging layer, each of said platforms having formed thereon a ball of said ball grid array; and

an adhesive layer overlying said silicon packaging layer and underlying said platforms,

wherein said platforms are bonded to said silicon packaging layer through said adhesive layer.

2. The chip-sized wafer level packaged device according to claim 1 , wherein said edge surfaces bound said chip, said bond pads being remote from said edge surfaces.

3. The chip-sized wafer level packaged device according to claim 2 , wherein the edge surfaces are exposed.

4. The chip-sized wafer level packaged device according to claim 1 , wherein said compliant layer comprises silicone.

5. The chip-sized wafer level packaged device according to claim 1 , wherein said device is a DRAM device.

6. The chip-sized wafer level packaged device according to claim 1 , wherein said semiconductor wafer contains at least one of silicon and Gallium Arsenide.

7. The chip-sized wafer level packaged device according to claim 1 , wherein said silicon packaging layer is adhered to said portion of said semiconductor wafer by an adhesive, said adhesive having thermal expansion characteristics similar to those of said packaging layer.

8. The chip-sized wafer level packaged device according to claim 1 and wherein said packaging layer comprises silicon.

9. The chip-sized wafer level packaged device according to claim 1 , further comprising metal connections formed over said compliant layer and underlying said ball grid array, said metal connections providing electrical connection between said ball grid array and said device.

10. The chip-sized wafer level packaged device according to claim 1 , further comprising alpha-particle shielding provided between said ball grid array and said device.

11. The chip-sized wafer level packaged device according to claim 10 , wherein said alpha-particle shielding is provided by at least one second compliant layer formed over said packaging layer and underlying said ball grid array.

12. The chip-sized wafer level packaged device according to claim 11 , wherein said at least one second compliant layer is said insulating layer.

13. The chip-sized wafer level packaged device according to claim 1 and wherein said device includes a memory device.

14. A chip-sized wafer level packaged device comprising:

a chip embodying a device, said chip having a surface and bond pads at said surface;

a chip-sized silicon packaging layer overlying said surface of said chip, said packaging layer comprising a material having thermal expansion characteristics similar to those of said semiconductor wafer, the silicon packaging layer having a surface facing away from said chip, and openings extending through said packaging layer at locations overlying said bond pads, the chip and the packaging layer having edge surfaces extending away from the surface of the chip and the surface of the packaging layer, respectively;

a ball grid array formed over said surface of said packaging layer and being electrically coupled to said bond pads; and

an insulating layer coating inner surfaces of at least some of the openings.

15. The chip-sized wafer level packaged device according to claim 14 , wherein the edge surfaces are exposed.

16. The chip-sized wafer level packaged device according to claim 14 , wherein the edge surfaces define a common plane.

17. The chip-sized wafer level packaged device according to claim 14 , wherein said edge surfaces bound said chip, said bond pads being remote from said edge surfaces.

18. A chip-sized wafer level packaged device comprising:

a chip embodying a device, said chip having a front surface, an opposed rear surface, and bond pads exposed at said front surface;

a chip-sized silicon packaging layer overlying said rear surface of said chip, said packaging layer comprising a material having thermal expansion characteristics similar to those of said semiconductor wafer, the silicon packaging layer having a surface facing away from said chip, and openings extending through said packaging layer at locations overlying said bond pads;

a ball grid array formed over said surface of said packaging layer and being electrically coupled to said bond pads; and

an insulating layer coating inner surfaces of at least some of the openings.

19. The chip-sized wafer level packaged device of claim 18 , wherein the chip and the packaging layer having edge surfaces extending away from the surface of the chip and the surface of the packaging layer, respectively, the edge surfaces being exposed.

20. The chip-sized wafer level packaged device of claim 18 , further comprising another chip sized silicon packaging layer overlying said front surface of said chip.