Microelectronic packages with dual or multiple-etched flip-chip connectors
View Patent ↗A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
1. A packaged microelectronic element, comprising:
a microelectronic element having a front surface and a plurality of solid metal posts extending away from the front surface; and
a substrate having a major surface and a plurality of conductive elements exposed at the major surface, the conductive elements being joined to the solid metal posts;
each solid metal post including a base region adjacent the microelectronic element and a tip region, remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces;
each solid metal post having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
2. The packaged microelectronic element of claim 1 , wherein each solid metal post further includes at least one intermediate region located between the base region and the top region, the intermediate region having a concave circumferential surface, the horizontal dimension of each solid metal post being a third function of vertical location in the intermediate region.
3. The packaged microelectronic element of claim 1 , wherein each solid metal post has a width in a direction of the front surface and a height extending from the front surface, wherein the height is at least half of the width.
4. The packaged microelectronic element of claim 1 , wherein the solid metal posts are joined to the conductive elements with a fusible metal.
5. The packaged microelectronic element of claim 4 , wherein the fusible metal comprises solder, and the solder covers at least portions of edge surfaces of each solid metal post.
6. The packaged microelectronic element of claim 5 , further comprising a plurality of conductive pads located at the front surface, wherein each solid metal post extends from a respective one of the plurality of conductive pads and the solder does not touch at least one of the plurality of conductive pads.
7. The packaged microelectronic element of claim 5 , wherein the solder does not touch the base region of any solid metal post.
8. The packaged microelectronic element of claim 4 , wherein the fusible metal comprises solder, and the solder touches only a top surface of each solid metal post.
9. The packaged microelectronic element of claim 1 , wherein a height of each solid metal post is between 25% and 50% of the distance between the front surface of the microelectronic element and the major surface of the substrate.
10. The packaged microelectronic element of claim 1 , wherein a height of each solid metal post is at least 40% of the distance between the front surface of the microelectronic element and the major surface of the substrate.
11. The packaged microelectronic element of claim 1 , wherein the solid metal posts and the conductive elements are diffusion-bonded together.
12. The packaged microelectronic element of claim 1 , wherein the first and second functions are substantially different.
13. The packaged microelectronic element of claim 1 , wherein a slope of horizontal dimension versus vertical location changes abruptly at a boundary between the base and the tip regions of the solid metal posts.
14. The packaged microelectronic element of claim 1 , wherein the solid metal posts and the conductive elements consist essentially of copper.
15. The packaged microelectronic element of claim 1 , wherein the conductive elements include conductive pads, the pads being joined to the solid metal posts.
16. The packaged microelectronic element of claim 1 , wherein the solid metal posts are first solid metal posts and the conductive elements include a plurality of second solid metal posts extending above the major surface and joined to the first solid metal posts, the second posts having top surfaces remote from the major surface of the substrate and edge surfaces extending at substantial angles away from the top surfaces.
17. The packaged microelectronic element of claim 16 , wherein the first solid metal posts are joined to the second solid metal posts with a fusible metal.
18. The packaged microelectronic element of claim 17 , wherein the fusible metal comprises solder, and the solder covers at least portions of edge surfaces of each solid metal post.
19. The packaged microelectronic element of claim 18 , further comprising a plurality of conductive pads located at the front surface, wherein each first solid metal post extends from a respective one of the plurality of conductive pads and the solder does not touch at least one of the plurality of conductive pads.
20. The packaged microelectronic element of claim 17 , wherein the fusible metal comprises solder, and the solder touches only a top surface of each solid metal post.
21. The packaged microelectronic element of claim 16 , wherein the first and second solid metal posts are diffusion-bonded together.
22. The packaged microelectronic element of claim 16 , wherein each second solid metal post includes a base region adjacent the substrate and a tip region, remote from the substrate, the base region and tip region of each second solid metal post having respective concave circumferential surfaces, each second solid metal post having a horizontal dimension which is a third function of vertical location in the base region and which is a fourth function of vertical location in the tip region.
23. The packaged microelectronic element of claim 22 , wherein each second post has a width in a direction of the major surface and a height extending from the major surface, wherein the height is at least half of the width.
24. The packaged microelectronic element of claim 22 , wherein the first solid metal posts are joined to the second solid metal posts with a fusible metal.
25. The packaged microelectronic element of claim 24 , wherein the fusible metal comprises solder, and the solder covers at least portions of edge surfaces of each solid metal post.
26. The packaged microelectronic element of claim 25 , further comprising a plurality of conductive pads located at the front surface, wherein each first solid metal post extends from a respective one of the plurality of conductive pads and the solder does not touch at least one of the plurality of conductive pads.
27. The packaged microelectronic element of claim 25 , wherein the solder does not touch the base region of any solid metal post.
28. The packaged microelectronic element of claim 24 , wherein the fusible metal comprises solder, and the solder touches only a top surface of each solid metal post.
29. The packaged microelectronic element of claim 22 , wherein the first and second solid metal posts are diffusion-bonded together.
30. The packaged microelectronic element of claim 22 , wherein the first function is the same as the third function and the second function is the same as the fourth function.
31. A packaged microelectronic element, comprising:
a microelectronic element having a front surface and a plurality of first solid metal posts projecting above the front surface, the first posts having top surfaces remote from the front surface and edge surfaces extending at substantial angles away from the front surface; and
a substrate having a major surface and a plurality of second solid metal posts extending from the major surface and joined to the first solid metal posts;
each second solid metal post including a base region adjacent the microelectronic element and a tip region, remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces;
each second solid metal post having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
32. The packaged microelectronic element of claim 31 , wherein each first post has a frustoconical shape.
33. The packaged microelectronic element of claim 31 , wherein each second post has a width in a direction of the major surface and a height extending from the major surface, wherein the height is at least half of the width.
34. The packaged microelectronic element of claim 31 , wherein the first solid metal posts are joined to the second solid metal posts with a fusible metal.
35. The packaged microelectronic element of claim 34 , wherein the fusible metal comprises solder, and the solder covers at least portions of edge surfaces of each solid metal post.
36. The packaged microelectronic element of claim 35 , further comprising a plurality of conductive pads located at the front surface, wherein each first solid metal post extends from a respective one of the plurality of conductive pads and the solder does not touch at least one of the plurality of conductive pads.
37. The packaged microelectronic element of claim 34 , wherein the fusible metal comprises solder, and the solder touches only a top surface of each solid metal post.
38. The packaged microelectronic element of claim 31 , wherein the first and second solid metal posts are diffusion-bonded together.
39. A method of assembling a packaged microelectronic element comprising:
(a) providing a microelectronic element having a front surface and a plurality of solid metal posts projecting in a vertical direction above the front surface, each solid metal post including a base region adjacent the front surface and a tip region, remote from the front surface, the base region and the tip region having respective concave circumferential surfaces, each solid metal post having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region;
(b) at least substantially aligning the plurality of solid metal posts with a plurality of conductive elements exposed at a major surface of a substrate; and
(c) joining the solid metal posts of the microelectronic element with the conductive elements of the substrate.
40. The method of claim 39 , wherein step (c) includes heating a fusible metal to a melting temperature, wherein the fusible metal flows onto exposed portions of edge surfaces of the solid metal posts.
41. The method of claim 40 , wherein the fusible metal comprises solder, and the solder covers at least portions of edge surfaces of each solid metal post.
42. The method of claim 41 , further comprising a plurality of conductive pads located at the front surface, wherein each solid metal post extends from a respective one of the plurality of conductive pads and the solder does not touch at least one of the plurality of conductive pads.
43. The method of claim 41 , wherein the solder does not touch the base region of any solid metal post.
44. The method of claim 40 , wherein the fusible metal comprises solder, and the solder touches only a top surface of each solid metal post.
45. The method of claim 39 , wherein a height of each sold metal post is between 25% and 50% of the distance between the front surface of the microelectronic element and the major surface of the substrate.
46. The method of claim 39 , wherein a height of each sold metal post is at least 40% of the distance between the front surface of the microelectronic element and the major surface of the substrate.
47. The method of claim 39 , wherein a passivation layer and an underbump metallization layer are deposited over the microelectronic element.