Chip assembly including package element and integrated circuit chip
View Patent ↗The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.
1. An assembly, comprising:
a package element having a top surface;
an integrated circuit chip having a top surface, a bottom surface, and contacts exposed at the top surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;
at least one spacer element residing between the top surface of the package element and the bottom surface of the chip, the at least one spacer element forming a substantially closed cavity between the package element and the chip; and
first conductive features extending from the contacts of the chip along the top surface, extending along at least one edge surface of the chip and extending from the at least one edge surface of the chip to the top surface of the package element.
2. The assembly of claim 1 , further comprising a bonding material residing on at least some of the first conductive features.
3. The assembly of claim 1 , further comprising second conductive features extending along the package element.
4. The assembly of claim 3 , wherein the first and second conductive features are electrically connected.
5. The assembly of claim 3 , further comprising an antenna disposed within the cavity, the antenna being electrically connected to the second conductive features.
6. The assembly of claim 3 , further comprising elements operable to collectively function as a microelectromechanical system disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.
7. The assembly of claim 3 , further comprising elements operable to collectively function as a surface acoustic wave device disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.
8. The assembly of claim 1 , wherein the package element includes silicon.
9. The assembly of claim 1 , wherein the package element includes glass.
10. An assembly, comprising:
a package element having a top surface;
an integrated circuit chip having a top surface, a bottom surface, edge surfaces extending between the top and bottom surfaces and contacts exposed at the top surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;
at least one spacer element residing between the top surface of the package element and the bottom surface of the chip, the at least one spacer element forming a cavity between the package element and the integrated circuit chip; and
first conductive features extending from the contacts of the chip along the top surface, at least some of said first conductive features extending along at least one of the edge surfaces of the chip and at least some of the first conductive features extending from the at least one of the edge surfaces of the chip to the top surface of the package element.
11. The assembly of claim 10 , wherein the cavity is substantially closed.
12. The assembly of claim 10 , further comprising second conductive features extending between the package element and integrated circuit chip into the cavity.
13. The assembly of claim 10 , further comprising a bonding material residing on at least some of the first conductive features.
14. The assembly of claim 12 , wherein the first conductive features and the second conductive features are connected.
15. The assembly of claim 10 , further comprising an antenna disposed within the cavity, the antenna being electrically connected to the second conductive features.
16. The assembly of claim 10 , further comprising elements operable to collectively function as a microelectromechanical system disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.
17. The assembly of claim 10 , further comprising elements operable to collectively function as a surface acoustic wave device disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.
18. The assembly of claim 10 , wherein the package element includes silicon.
19. The assembly of claim 10 , wherein the package element includes glass.