Substrate for a microelectronic package and method of fabricating thereof
View Patent ↗Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.
1. A microelectronic substrate having a plurality of traces configured for coupling with external contacts of a microelectronic element mountable thereto, comprising:
a plurality of solid metal first contact pins, each first pin having a base and a tip;
a plurality of first conductive elements including conductive traces and conductive contact areas configured for electrical connection with the microelectronic element mountable thereto, at least some of the first conductive elements being coupled to the bases of the first pins so that the first pins project downwardly from the first conductive elements; and
a molded dielectric layer disposed in regions around the first pins and contacting the first pins, the molded dielectric layer having an exposed bottom surface coplanar with the tips of the first pins, and a top surface opposed to the bottom surface, wherein the first conductive elements extend along the top surface of the molded dielectric layer, and at least some of the tips of the first pins are exposed at the bottom surface of the dielectric layer, wherein the molded dielectric layer comprises epoxy.
2. The substrate of claim 1 wherein the molded dielectric layer further comprises an additive which influences properties of the molded dielectric layer.
3. The substrate of claim 2 wherein the additive includes a particulate material.
4. The substrate of claim 2 wherein the additive includes fibrous reinforcements.
5. The substrate of claim 4 wherein the fibrous reinforcements include glass fibers.
6. The substrate of claim 1 wherein the top surface of the molded dielectric layer is coplanar with the bases of the first pins, and the first conductive traces extend over the top surface of said dielectric layer.
7. The substrate of claim 1 wherein different ones of said first pins have different form factors.
8. The substrate of claim 1 further comprising a solid metal spacer extending in at least one direction parallel to the top and bottom surfaces of the molded dielectric layer, said spacer having a dimension in said at least one direction greater than a distance between two adjacent first pins of said first pins, said spacer having a top surface coplanar with said top surface of said molded dielectric layer and having a bottom edge coplanar with said bottom surface of said molded dielectric layer and said tips of said first pins.
9. The substrate of claim 8 further comprising second conductive elements including second conductive traces and second contact areas electrically coupled with said spacer.
10. The substrate of claim 8 wherein at least one of said second conductive elements has width in a second direction parallel to said top surface of said molded dielectric layer which is greater than a width of at least one other of said second conductive elements in said second direction.
11. The substrate of claim 8 wherein at least one of the spacer or the first conductive elements include an electrically conductive principal metal and a conductive barrier layer disposed between the principal metal and the bases of at least one of the spacer and the first pins.
12. The substrate of claim 11 wherein the barrier layer is formed from Ni.
13. The substrate of claim 11 wherein the principal metal comprises copper.
14. The substrate of claim 1 wherein different ones of said first pins have different form factors.
15. A microelectronic substrate having a plurality of traces for electrical interconnection with external contacts of a microelectronic element mountable thereto, comprising:
a plurality of solid metal first contact pins, each first pin having a base and a tip;
a plurality of first conductive elements including conductive traces and conductive contact areas adapted for electrical connection with the microelectronic element mountable thereto, at least some of the first conductive elements being coupled to the bases of the first pins so that the first pins project downwardly from the first conductive elements;
a molded dielectric layer disposed in regions around the first pins and contacting the first pins, the molded dielectric layer having an exposed bottom surface coplanar with the tips of the first pins, a top surface opposed to the bottom surface, wherein the first conductive elements extend along the top surface of the molded dielectric layer, and at least some of the tips of the first pins are exposed at the bottom surface of the molded dielectric layer; and
a solid metal spacer extending in a first direction parallel to the top and bottom surfaces of the molded dielectric layer, said spacer having a dimension in said first direction greater than a distance between two adjacent first pins of said first pins, said spacer having a top surface coplanar with said top surface of said molded dielectric layer and having a bottom edge coplanar with said bottom surface of said molded dielectric layer and said tips of said first pins.
16. The substrate of claim 15 further comprising second conductive elements including second conductive traces and second contact areas electrically coupled with said spacer.
17. The substrate of claim 15 wherein at least one of said second conductive elements has width in a second direction parallel to said top surface of said molded dielectric layer which is greater than a width of at least one other of said second conductive elements in said second direction.
18. The substrate of claim 15 wherein the first conductive elements and the spacer include an electrically conductive principal metal and a conductive barrier layer disposed between the principal metal and the bases of the first pins.
19. The substrate of claim 18 wherein the barrier layer is formed from Ni.
20. The substrate of claim 15 further comprising a plurality of bottom traces extending over said bottom surface of said molded dielectric layer, at least some of said bottom traces being coupled to at least some of the tip ends of said first pins.
21. A unit comprising the substrate of claim 15 and at least one microelectronic element, said microelectronic element being electrically coupled to at least some of said first pins by at least some of said first traces.
22. An assembly including a plurality of units as claimed in claim 21 stacked in superposed arrangement with the tip ends of the first pins in a higher unit in the stack electrically connected to the first pins of a lower unit in the stack.
23. The microelectronic substrate of claim 15 wherein the molded dielectric layer is formed by introducing a flowable composition between the first pins and curing the same.
24. The microelectronic substrate of claim 15 wherein the first pins and the spacer are formed by etching a metal plate.
25. The microelectronic substrate of claim 15 wherein the first conductive elements are formed by etching a metal layer overlying at least some of said first pins and said spacer.
26. The microelectronic substrate of claim 15 wherein the spacer is configured to provide electrical connection through the substrate in a direction of the substrate's thickness.