IP Library Granted Patent US 8,802,502
Granted Patent B2
US 8,802,502 · App. 14/052,037 · Granted Aug 12, 2014

TSOP with impedance control

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Quick Facts
Patent No.
US 8,802,502
App. No.
14/052,037
Granted
Aug 12, 2014
Kind
B2
Abstract

A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

Claims (30)

1. A method of fabricating a semiconductor device comprising:

attaching a lead frame to a die, the lead frame including a plurality of leads having at least substantial portions arranged in a lead plane extending over a surface of the die;

positioning at least a substantial portion of one conductive element arranged in a plane adjacent the lead frame and substantially parallel to the lead plane such that the conductive element is capacitively coupled to the lead frame and the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path;

providing respective electrical connections between the leads and the die and the conductive elements; and

encapsulating the leads and the conductive element with an encapsulant, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the controlled-impedance conduction path has a length of at least one millimeter.

2. A method of fabricating a semiconductor device comprising:

attaching a lead frame to a die, the lead frame including a plurality of leads having at least substantial portions arranged in a lead plane extending over a surface of the die;

positioning at least a substantial portion of one conductive element arranged in a plane adjacent the lead frame and substantially parallel to the lead plane such that the conductive element is capacitively coupled to the lead frame and the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path;

providing respective electrical connections between the leads and the die and the conductive elements; and

encapsulating the leads and the conductive element with an encapsulant, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the substantial portion of one conductive element has a length of at least 25% of the total length of the conductive element.

3. A method of fabricating a semiconductor device comprising:

attaching a lead frame to a die, the lead frame including a plurality of leads having at least substantial portions arranged in a lead plane extending over a surface of the die;

positioning at least a substantial portion of one conductive element arranged in a plane adjacent the lead frame and substantially parallel to the lead plane such that the conductive element is capacitively coupled to the lead frame and the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path;

providing respective electrical connections between the leads and the die and the conductive elements; and

encapsulating the leads and the conductive element with an encapsulant, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the die has a front surface and a distance between the plane of the conductive element and the lead plane is equal to or smaller than a distance between the plane of the conductive element and the front surface of the die.

4. A method of fabricating a semiconductor device comprising:

attaching a lead frame to a die, the lead frame including a plurality of leads having at least substantial portions arranged in a lead plane extending over a surface of the die;

positioning at least a substantial portion of one conductive element arranged in a plane adjacent the lead frame and substantially parallel to the lead plane such that the conductive element is capacitively coupled to the lead frame and the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path;

providing respective electrical connections between the leads and the die and the conductive elements; and

encapsulating the leads and the conductive element with an encapsulant, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the die has a front surface and a distance between the plane of the conductive element and the lead plane is equal to or smaller than a distance between the lead plane and the front surface of the die.

5. A method of fabricating a semiconductor device comprising:

attaching a lead frame to a die, the lead frame including a plurality of leads having at least substantial portions arranged in a lead plane extending over a surface of the die;

positioning at least a substantial portion of one conductive element arranged in a plane adjacent the lead frame and substantially parallel to the lead plane such that the conductive element is capacitively coupled to the lead frame and the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path;

providing respective electrical connections between the leads and the die and the conductive elements; and

encapsulating the leads and the conductive element with an encapsulant, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein encapsulating the leads and the conductive element with an encapsulant comprises placing the device in a mold having at least two parts, closing the mold such that the parts engage each other and the connection regions, and filling a space defined by the closed mold with the encapsulant.

Assignments (7)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0661 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2014
From: TESSERA RESEARCH LLC
To: TESSERA, INC.
Reel/Frame 032452/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2014
From: HABA, BELGACEM; MARCUCCI, BRIAN
To: TESSERA RESEARCH LLC
Reel/Frame 032441/0554 →