Packaged semiconductor chips with array
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.
1. Stacked chip-sized, wafer level packaged devices comprising:
at least first and second chip-sized wafer level packaged devices each including:
a portion of a semiconductor wafer including a device;
at least one packaging layer containing silicon and formed over said device;
a first ball grid array at a first package surface and formed over a surface of said at least one packaging layer and being electrically connected to said device, the first package surface facing in a first direction; and
a second ball grid array at a second package surface and formed over a surface of said portion of said semiconductor wafer and being electrically connected to said device, the second package surface facing in a second direction opposite the first direction,
wherein said first ball grid array of said first chip-sized wafer level packaged device is coupled to said second ball grid array of said second chip-sized wafer level packaged device, and the first package surface of the first chip-sized wafer level packaged device faces the second package surface of the second chip-sized wafer level packaged device.
2. Stacked chip-sized, wafer level packaged devices according to claim 1 and wherein said at least one packaging layer comprises a plurality of packaging layers.
3. Stacked chip-sized, wafer level packaged devices according to claim 2 and wherein said plurality of packaging layers are disposed on the same side of said portion of said semiconductor wafer.
4. Stacked chip-sized, wafer level packaged devices according to claim 2 , wherein said plurality of packaging layers comprise a first packaging layer formed over a first surface of said semiconductor wafer and a second packaging layer formed over a second surface of said semiconductor wafer.
5. Stacked chip-sized, wafer level packaged devices according to claim 4 , further comprising:
a first compliant layer formed on said first packaging layer and underlying said first ball grid array;
a second compliant layer formed on said second packaging layer and underlying said second ball grid array.
6. Stacked chip-sized, wafer level packaged devices according to claim 5 , wherein at least one of said compliant layers provides alpha-particle shielding between said first and second ball grid arrays and said device.
7. Stacked chip-sized, wafer level packaged devices according to claim 5 , wherein at least one of said compliant layers comprises a layer of an electrophoretic material.
8. Stacked chip-sized, wafer level packaged device according to claim 1 and wherein said device is a DRAM device.
9. Stacked chip-sized, wafer level packaged devices comprising:
at least first and second chip-sized wafer level packaged devices each including:
a portion of a semiconductor wafer including a device;
at least one packaging layer formed over said device;
a first ball grid array at a first package surface and formed over a surface of said at least one packaging layer and being electrically coupled to said device, the first package surface facing in a first direction;
a second ball grid array at a second package surface and formed over a surface of said portion of said semiconductor wafer and being electrically coupled to said device, the second package surface facing in a second direction opposite the first direction; and
a compliant electrophoretic coating layer underlying at least one of said first and second ball grid arrays,
wherein said first ball grid array of said first chip-sized wafer level packaged device is coupled to said second ball grid array of said second chip-sized wafer level packaged device, and the first package surface of the first chip-sized wafer level packaged device faces the second package surface of the second chip-sized wafer level packaged device.
10. Stacked chip-sized, wafer level packaged devices according to claim 9 and wherein said at least one packaging layer contains silicon.
11. Stacked chip-sized, wafer level packaged devices according to claim 9 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between said first and second ball grid arrays and said device.
12. Stacked chip-sized, wafer level packaged devices according to claim 9 and wherein said device is a DRAM device.
13. Stacked chip-sized, wafer level packaged devices according to claim 9 , wherein said at least one packaging layer comprises:
a first packaging layer formed on a first surface of said semiconductor wafer and underlying said first ball grid array;
a second packaging layer formed on a second surface of said semiconductor wafer and underlying said second ball grid array.
14. Stacked chip-sized, wafer level packaged devices according to claim 13 , wherein said compliant electrophoretic coating layer provides alpha-particle shielding between at least one of said first and second ball grid arrays and said device.
15. Stacked chip-sized, wafer level packaged devices according to claim 13 , wherein said compliant electrophoretic coating comprises a first compliant electrophoretic coating layer formed on said first packaging layer and a second compliant electrophoretic coating layer formed on said second packaging layer.