Stackable molded microelectronic packages

1. A microelectronic package comprising:

a substrate having a first surface and a second surface remote from the first surface;

a microelectronic element overlying the first surface;

substantially rigid conductive posts projecting above at least one of the first or second surfaces, the conductive posts having top surfaces remote from the substrate and edge surfaces extending away from the top surfaces;

conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project, the conductive elements being electrically interconnected with the microelectronic element; and

an encapsulant overlying at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a plurality of openings each exposing the top surface and partially exposing the edge surface of at least one of the conductive posts, wherein at least some of the conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials.

2. The microelectronic package as claimed in claim 1 , wherein the conductive posts project to a first height above at least one of the first or second surfaces, the encapsulant contacts the conductive posts and has a major surface at a second height above the same surface of the substrate above which the conductive posts project, the second height being greater than the first height, wherein the openings in the encapsulant are openings in the major surface.

3. The microelectronic package as claimed in claim 2 , wherein the conductive posts project above the first surface and the conductive elements are exposed at the second surface.

4. The microelectronic package as claimed in claim 3 , wherein the first surface has a first region and a second region extending from the first region, the microelectronic element overlies the first region, and the posts are aligned with the second region.

5. The microelectronic package as claimed in claim 2 , wherein the conductive posts project above the second surface and the conductive elements are exposed at the first surface.

6. The microelectronic package as claimed in claim 4 , wherein the major surface of the encapsulant is a substantially planar surface, the encapsulant further having a second surface overlying the microelectronic element at a third height above the first surface, the third height being different from the second height.

7. The microelectronic package as claimed in claim 6 , wherein the third height is greater than the second height.

8. The microelectronic package as claimed in claim 4 , wherein the major surface of the encapsulant is a substantially planar surface overlying the first and second regions of the first surface at an at least substantially uniform second height therefrom and overlying the microelectronic element.

9. The microelectronic package as claimed in claim 2 , wherein at least one conductive post includes a tip region remote from the microelectronic element and a second region disposed below the tip region and closer to the substrate, the second region and tip region having respective concave circumferential surfaces, and the at least one post consisting essentially of metal and having a horizontal dimension which is a first function of vertical location in the tip region and which is a second function of vertical location in the second region.

10. The microelectronic package as claimed in claim 3 , wherein the conductive elements include at least one of conductive posts or masses of conductive bonding material, and a portion of the encapsulant overlies the second surface and further has a plurality of second openings, each partially exposing at least one of the conductive elements, wherein at least some of the conductive elements are electrically insulated from one another and adapted to simultaneously carry different electric potentials.

11. The microelectronic package as claimed in claim 2 , wherein surfaces of at least two of the conductive posts are at least partially exposed within a single one of the openings.

12. A microelectronic package comprising:

a substrate having a first surface and a second surface remote from the first surface;

a microelectronic element overlying the first surface;

substantially rigid conductive posts projecting above at least one of the first or second surfaces, the conductive posts having top surfaces remote from the substrate and edge surfaces extending away from the top surfaces;

conductive masses joined to the conductive posts;

conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project, the conductive elements being electrically interconnected with the microelectronic element; and

an encapsulant overlying at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a plurality of openings each partially exposing at least one of the conductive masses joined to the conductive posts, wherein at least some of the conductive masses are electrically insulated from one another and adapted to simultaneously carry different electric potentials,

wherein the conductive masses project to a first height above at least one of the first or second surfaces, the encapsulant contacts the conductive masses and has a major surface at a second height above the same surface of the substrate above which the conductive masses project, the second height being greater than the first height, wherein the openings in the encapsulant are openings in the major surface,

wherein surfaces of at least two of the conductive masses are at least partially exposed within a single one of the openings.

13. A microelectronic package comprising:

a substrate having a first surface and a second surface remote from the first surface;

a microelectronic element overlying the first surface;

substantially rigid conductive posts projecting above at least one of the first or second surfaces, the conductive posts having top surfaces remote from the substrate and edge surfaces extending away from the top surfaces;

conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project, the conductive elements being electrically interconnected with the microelectronic element; and

an encapsulant overlying at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a plurality of openings each partially exposing the top surface of at least one of the conductive posts, wherein at least some of the conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials,

wherein the conductive posts project to a first height above at least one of the first or second surfaces, the encapsulant contacts the conductive posts and has a major surface at a second height above the same surface of the substrate above which the conductive posts project, the second height being greater than the first height, wherein the openings in the encapsulant are openings in the major surface,

wherein at least one conductive post includes a tip region remote from the microelectronic element and a second region disposed below the tip region and closer to the substrate, the second region and tip region having respective concave circumferential surfaces, and the at least one post consisting essentially of metal and having a horizontal dimension which is a first function of vertical location in the tip region and which is a second function of vertical location in the second region.

14. A microelectronic package comprising:

a substrate having a first surface and a second surface remote from the first surface;

a microelectronic element overlying the first surface;

substantially rigid conductive posts projecting above at least one of the first or second surfaces, the conductive posts having top surfaces remote from the substrate and edge surfaces extending away from the top surfaces;

conductive masses joined to the conductive posts;

conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project, the conductive elements being electrically interconnected with the microelectronic element; and

an encapsulant overlying at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a plurality of openings each partially exposing at least one of the conductive masses joined to the conductive posts, wherein at least some of the conductive masses are electrically insulated from one another and adapted to simultaneously carry different electric potentials,

wherein the conductive masses project to a first height above at least one of the first or second surfaces, the encapsulant contacts the conductive masses and has a major surface at a second height above the same surface of the substrate above which the conductive masses project, the second height being greater than the first height, wherein the openings in the encapsulant are openings in the major surface,

wherein at least one conductive post includes a tip region remote from the microelectronic element and a second region disposed below the tip region and closer to the substrate, the second region and tip region having respective concave circumferential surfaces, and the at least one post consisting essentially of metal and having a horizontal dimension which is a first function of vertical location in the tip region and which is a second function of vertical location in the second region.

15. A microelectronic package comprising:

a substrate having a first surface and a second surface remote from the first surface;

a microelectronic element overlying the first surface;

substantially rigid conductive posts projecting above at least one of the first or second surfaces, the conductive posts having top surfaces remote from the substrate and edge surfaces extending away from the top surfaces;

conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project, the conductive elements being electrically interconnected with the microelectronic element; and

an encapsulant overlying at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a plurality of openings each partially exposing the top surface of at least one of the conductive posts, wherein at least some of the conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials,

wherein the conductive posts project to a first height above at least one of the first or second surfaces, the encapsulant contacts the conductive posts and has a major surface at a second height above the same surface of the substrate above which the conductive posts project, the second height being greater than the first height, wherein the openings in the encapsulant are openings in the major surface,

wherein surfaces of at least two of the conductive posts are at least partially exposed within a single one of the openings.