IP Library Granted Patent US 8,759,973
Granted Patent B2
US 8,759,973 · App. 13/335,022 · Granted Jun 24, 2014

Microelectronic assemblies having compliancy and methods therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,759,973
App. No.
13/335,022
Granted
Jun 24, 2014
Kind
B2
Abstract

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Claims (32)

1. A microelectronic assembly comprising:

a semiconductor wafer having a first surface and contacts accessible at the first surface;

a plurality of compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, the plurality of compliant bumps having coplanar top surfaces;

conductive traces electrically connected with the contacts and extending therefrom to overlie the coplanar top surfaces of the compliant bumps;

a first dielectric layer having openings and overlying the conductive traces;

a second dielectric layer overlying the first surface of the semiconductor wafer and at least edges of the compliant bumps; and

conductive elements overlying the coplanar top surfaces, the conductive elements extending through the openings in the first dielectric layer and in contact with the conductive traces.

2. The assembly as claimed in claim 1 , wherein the conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

3. The assembly as claimed in claim 1 , further comprising a circuit panel, wherein the conductive elements include terminals of the assembly for electrical connection with corresponding contact elements of the circuit panel.

4. The assembly as claimed in claim 3 , wherein the terminals include at least one terminal which is disposed singly atop one of the plurality of compliant bumps.

5. The assembly as claimed in claim 3 , wherein the terminals are bonded to the contact elements of the circuit panel.

6. The assembly as claimed in claim 1 , wherein the semiconductor wafer comprises one or more memory chips.

7. The assembly as claimed in claim 1 , wherein the conductive elements are rigid solid metal posts.

8. The assembly as claimed in claim 7 , wherein the rigid solid metal posts are frustoconical.

9. The assembly as claimed in claim 7 , wherein the rigid solid metal posts are plated posts.

10. The assembly as claimed in claim 7 , wherein the rigid solid metal posts have a height above the top surface of the compliant layer ranging from 50-300 micrometers.

11. A microelectronic assembly comprising:

a semiconductor wafer having a first surface and contacts accessible at the first surface;

compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, each of the compliant bumps having a planar top surface;

a first dielectric layer overlying the first surface of the semiconductor wafer and at least edges of the compliant bumps, wherein the planar top surfaces of the compliant bumps and the contacts are accessible through the dielectric layer;

conductive traces electrically connected with the contacts and extending therefrom to overlie the planar top surfaces of the compliant bumps;

a second dielectric layer having openings, portions of the conductive traces being exposed through the openings; and

conductive elements overlying the planar top surfaces in contact with the conductive traces.

12. The assembly as claimed in claim 11 , wherein the first dielectric layer includes a photoimageable material.

13. The assembly as claimed in claim 12 , wherein the photoimageable material includes silicone.

14. The assembly as claimed in claim 11 , wherein the first dielectric layer is compliant.

15. The assembly as claimed in claim 11 , wherein the conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

16. The assembly as claimed in claim 11 , further comprising a circuit panel, wherein the conductive elements include terminals of the assembly for electrical connection with corresponding contact elements of a circuit panel.

17. The assembly as claimed in claim 16 , wherein the terminals include at least one terminal which is disposed singly atop one of the compliant bumps.

18. The assembly, as claimed in claim 11 , wherein the conductive elements are rigid solid metal posts.

19. The assembly as claimed in claim 18 , wherein the conductive posts are frustoconical.

20. The assembly as claimed in claim 18 , wherein the conductive posts have a height above the top surface of the compliant layer ranging from 50-300 micrometers.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0661 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2013
From: OGANESIAN, VAGE; GAO, GUILIAN; HABA, BELGACEM; OVRUTSKY, DAVID
To: TESSERA, INC.
Reel/Frame 031347/0702 →