Microelectronic assemblies having compliancy and methods therefor
View Patent ↗A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.
1. A microelectronic assembly comprising:
a semiconductor wafer having a first surface and contacts accessible at the first surface;
compliant bumps of dielectric material overlying the first surface of said semiconductor wafer, each said compliant bump having a planar top surface;
a dielectric layer overlying the first surface of said semiconductor wafer and at least edges of said compliant bumps, wherein the planar top surfaces of said compliant bumps and said contacts are accessible through said dielectric layer;
conductive traces electrically connected with said contacts and extending therefrom to overlie the planar top surfaces of said compliant bumps; and
conductive elements overlying the planar top surfaces in contact with said conductive traces.
2. The assembly as claimed in claim 1 , wherein said conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.
3. The assembly as claimed in claim 1 , further comprising a circuit panel, wherein said conductive elements are terminals of said assembly for electrical connection with corresponding contact elements of the circuit panel.
4. The assembly as claimed in claim 3 , wherein said terminals include at least one terminal which is disposed singly atop one of said compliant bumps.
5. The assembly as claimed in claim 3 , wherein said terminals are bonded to said contact elements of said circuit panel.
6. The assembly as claimed in claim 5 , wherein said terminals are solder bonded to said contact elements.
7. The assembly as claimed in claim 1 , wherein said semiconductor wafer comprises one or more memory chips.
8. The assembly as claimed in claim 7 , wherein said wafer comprises one or more double-data-rate (DDR) chips.
9. The assembly as claimed in claim 1 , wherein the dielectric layer overlies the planar top surfaces of at least some of the compliant bumps and the conductive elements overlie the dielectric layer above the planar top surfaces.
10. The assembly as claimed in claim 1 , further comprising openings in the dielectric layer aligned with the planar top surfaces, wherein the conductive elements are disposed within the openings.
11. The assembly as claimed in claim 1 , further comprising a solder mask overlying the traces.
12. The assembly as claimed in claim 1 , wherein the conductive elements include solder balls.
13. The assembly as claimed in claim 1 , wherein the conductive elements include conductive posts.
14. The assembly as claimed in claim 1 , wherein the conductive elements include conductive pins.
15. The assembly as claimed in claim 1 , wherein the dielectric layer is a polymeric layer.
16. The assembly as claimed in claim 1 , wherein the dielectric layer includes a photoimageable material.
17. The assembly as claimed in claim 16 , wherein the photoimageable material includes silicone.
18. The assembly as claimed in claim 1 , wherein the dielectric layer is compliant.
19. The assembly as claimed in claim 1 , wherein two or more of said conductive elements are disposed atop a single one of said compliant bumps.