IP Library Granted Patent US 8,022,527
Granted Patent B2
US 8,022,527 · App. 12/908,265 · Granted Sep 20, 2011

Edge connect wafer level stacking

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,022,527
App. No.
12/908,265
Granted
Sep 20, 2011
Kind
B2
Abstract

In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

Claims (18)

1. A stacked microelectronic package comprising:

a plurality of subassemblies including a first subassembly and a second subassembly underlying the first subassembly, each subassembly having a front face and a rear face remote from the front face, each of the first and second subassemblies including a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge, the second subassembly having a plurality of rear contacts exposed at the rear face and a plurality of rear traces extending from the rear contacts about the at least one edge to at least some of the plurality of front contacts of at least one of the first or second subassemblies, and a substrate underlying the second subassembly, the substrate having a relief channel aligned with the at least one edge of each subassembly.

2. The stacked microelectronic package as claimed in claim 1 , further comprising a polymer material disposed in the relief channel, wherein at least one of the rear traces or the front traces overlie at least portions of the polymer material.

3. The stacked microelectronic package as claimed in claim 1 , wherein each of the plurality of subassemblies includes at least one microelectronic chip.

4. An assembly including the stacked microelectronic package as claimed in claim 3 , further comprising a circuit panel having terminals conductively connected to at least some package contacts selected from the group consisting of the rear contacts of the second subassembly and front contacts of one subassembly of the plurality of subassemblies.

5. An assembly as claimed in claim 1 , further comprising an additional microelectronic chip joined to the stacked microelectronic package such that a face of the additional microelectronic chip confronts a face of one of the first and second subassemblies.

6. An assembly as claimed in claim 5 , wherein contacts of the additional microelectronic chip are wire-bonded to the front contacts of the one subassembly.

7. An assembly as claimed in claim 6 , further comprising conductive masses joining the contacts of the additional microelectronic chip to the front contacts of the one subassembly.

8. An assembly as claimed in claim 5 , wherein the additional microelectronic chip includes a microcontroller.

9. An assembly as claimed in claim 5 , wherein at least one of the microelectronic chips in the plurality of subassemblies is replaceable by the additional microelectronic chip by disconnecting the at least one microelectronic chip from ones of the front contacts of the one subassembly and connecting the additional microelectronic chip to the ones of the front contacts.

10. An assembly as claimed in claim 5 , further comprising bond wires, the bond wires conductively connecting the front contacts of the one subassembly to the terminals of the circuit panel.

11. An assembly as claimed in claim 10 , further comprising conductive masses joining the contacts of the additional microelectronic chip to the front contacts of the one subassembly.

12. An assembly as claimed in claim 5 , further comprising bond wires, the bond wires conductively connecting contacts of the additional microelectronic chip to the terminals of the circuit panel.

13. An assembly as claimed in claim 1 , further comprising conductive masses joining the terminals of the circuit panel to the exposed front contacts of the one subassembly.

14. An assembly as claimed in claim 13 , further comprising an additional microelectronic chip joined to the rear face of the second subassembly, the additional microelectronic chip having contacts conductively connected to terminals of the circuit panel.

15. An assembly as claimed in claim 14 , further comprising bond wires, the bond wires joining the contacts of the additional microelectronic chip to the terminals of the circuit panel.

16. An assembly as claimed in claim 1 , further comprising conductive masses joining the terminals of the circuit panel to the rear contacts of the second subassembly.

17. An assembly as claimed in claim 16 , further comprising an additional microelectronic chip having contacts in conductive communication with the front contacts of the one subassembly.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0661 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2010
From: HABA, BELGACEM; OGANESIAN, VAGE
To: TESSERA, INC.
Reel/Frame 025180/0704 →