IP Library Granted Patent US 8,505,199
Granted Patent B2
US 8,505,199 · App. 12/228,890 · Granted Aug 13, 2013

Method of fabricating an interconnection element having conductive posts

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,505,199
App. No.
12/228,890
Granted
Aug 13, 2013
Kind
B2
Abstract

An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed.

Claims (32)

1. A method of fabricating an interconnection element having raised conductive posts for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, comprising:

a) forming conductive posts within a plurality of holes of a first element, each conductive post including at least a metal liner lining a wall of a corresponding hole, each post having an end within the corresponding hole;

b) forming terminals in conductive communication with the conductive posts; the terminals being connected through a dielectric layer to the conductive posts; and

c) removing at least a portion of the first element to cause the ends of the conductive posts to project outwardly beyond a first major surface of the interconnection element.

2. The method as claimed in claim 1 , wherein the first element is removed by etching the first element selectively relative to the metal liner.

3. The method as claimed in claim 2 , wherein the first element includes a first metal and the metal liner includes a second metal, the second metal resisting attack by an etchant used to selectively etch the first element.

4. The method as claimed in claim 3 , wherein step (a) includes forming a second metal layer in contact with the metal liner within the holes.

5. The method as claimed in claim 4 , further comprising forming the metal liner by processing including plating.

6. The method as claimed in claim 4 , wherein the step of forming the second metal layer includes plating.

7. The method as claimed in claim 6 , wherein the second metal layer fills the holes.

8. The method as claimed in claim 4 , wherein the second metal layer includes the first metal.

9. The method as claimed in claim 8 , wherein the first metal is copper and the metal liner includes nickel.

10. The method as claimed in claim 1 , wherein the first element includes a metal sheet consisting essentially of copper and the holes have a pitch less than about 150 microns.

11. The method as claimed in claim 10 , wherein the first element is formed by laser drilling through holes in a metal sheet and joining a carrier to a face of the metal sheet to cover the through holes.

12. The method as claimed in claim 10 , wherein the first element is formed by mechanically forming through holes in a metal sheet and joining a carrier to a face of the metal sheet to cover the through holes.

13. The method as claimed in claim 10 , wherein the conductive posts have frusto-conical shape.

14. The method as claimed in claim 10 , wherein conductive posts have cylindrical shape.

15. The method as claimed in claim 1 , wherein the posts do not completely fill the holes of the first element.

16. The method as claimed in claim 1 , wherein step (a) further includes forming metal features extending away from the posts along at least one surface of the first element, the metal features defining at least one electrically conductive trace extending from at least one post.

17. The method as claimed in claim 16 , further comprising forming a dielectric layer atop the posts and the at least one trace, and forming at least one second metal layer extending through the dielectric layer and electrically connected with the metal layer.

18. The method as claimed in claim 17 , wherein the second metal layer is electrically connected with the at least one conductive trace.

19. The method as claimed in claim 17 , wherein step (b) includes forming a second dielectric layer overlying the second metal layer and forming a third metal layer extending through the second dielectric layer and electrically connected with the second metal layer.

20. The method as claimed in claim 1 , wherein step (b) is performed such that the terminals are exposed at a second major surface opposite the first major surface from which the conductive posts project outwardly.

21. A method of fabricating an interconnection element, comprising:

a) forming conductive posts within a plurality of respective blind holes of a first element, the first element including a first metal, each conductive post having a liner including a second metal lining the respective hole, a layer including a third metal contacting the liner within the hole, and an end located within the respective hole, the second metal being resistant to attack by an etchant which attacks the first metal;

b) forming terminals exposed at a bottom surface of the interconnection element, the terminals being in conductive communication with the conductive posts; and

c) selectively removing at least some of the first metal from the first element using the etchant to cause at least the ends of the conductive posts to protrude beyond a top surface of the interconnection element, the top surface being opposite the bottom surface.

22. The method as claimed in claim 21 , wherein the posts do not completely fill the holes of the first element.

23. The method as claimed in claim 21 , wherein step (a) further includes forming metal features extending away from the posts along at least one surface of the first element, the metal features defining at least one electrically conductive trace extending from at least one post.

24. The method as claimed in claim 23 , further comprising forming a dielectric layer atop the posts and the at least one trace, and forming at least one second metal layer extending through the dielectric layer and electrically connected with the metal layer.

25. The method as claimed in claim 24 , wherein the second metal layer is electrically connected with the at least one conductive trace.

26. The method as claimed in claim 24 , wherein step (b) includes forming a second dielectric layer overlying the second metal layer and forming a third metal layer extending through the second dielectric layer and electrically connected with the second metal layer.

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073657/0979 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0661 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2009
From: KWON, JINSU; ENDO, KIMITAKA; MORAN, SEAN
To: TESSERA, INC.
Reel/Frame 022265/0140 →