CMOS transistor junction regions formed by a CVD etching and deposition sequence
View Patent ↗This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
1. A method comprising:
removing a first portion of a substrate adjacent to a gate electrode to form a first junction region and a different second portion of the substrate adjacent to the gate electrode to form a second junction region in the substrate; and
forming an epitaxial thickness of a crystalline material in the first junction region and in the second junction region;
wherein removing and forming occur in the same chamber without breaking a seal of the chamber;
wherein removing comprises etching with at least one of a chlorine gas, a hydrochloric acid gas, a hydrogen gas, and a nitrogen gas.
2. The method of claim 1 , wherein removing comprises etching at a flow into the chamber of between 5 standard cubic centimeters per minute (SCCM) and 10 SCCM, at a temperature of between 500 and 800 degrees Celsius, for between 30 minutes and 90 minutes.
3. A method comprising:
removing a first portion of a substrate to form a first tip region in a first substrate surface adjacent to a gate electrode of the substrate;
removing a different second portion of a substrate to form a second tip region in a second substrate surface adjacent to the gate electrode of the substrate;
forming a material in the first and second tip regions; and
doping the material formed in the first and second tip regions;
wherein the first tip region defines a first facet having an angle of approximately 54.7 degrees with respect to a bottom surface of the gate electrode, and the second tip region defines a second facet having an angle of approximately 54.7 degrees with respect to the bottom surface.
4. The method of claim 3 , wherein the first facet and second facet form planes {1,1,1} according to conventional Miller index nomenclature.
5. The method of claim 3 , wherein the first facet forms a first plane having a normal vector of {−1,1,1} and the second facet forms a second plane having a normal vector of {1,1,1} with respect to a coordinate system having a first axial plane defined by the first substrate surface, a second axial plane defined by a sidewall surface of the gate electrode and a third axial plane defined by a plane perpendicular to the first and second axial planes.
6. The method of claim 3 , wherein removing comprises forming the first facet under and contacting a bottom surface of a gate dielectric formed between the gate electrode and a top surface of the substrate, and forming the second facet under and contacting the bottom surface of the gate dielectric.
7. The method of claim 3 , wherein the first facet comprises a first tip fabricated from deposited material formed under a bottom surface of a gate dielectric formed between the gate electrode and a top surface of the substrate, and the second facet comprises a second tip fabricated from deposited material formed under the bottom surface.
8. The method of claim 3 , wherein the substrate comprises a material of one of silicon, polycrystalline silicon, and single crystal silicon; and wherein forming comprises forming a thickness of one of boron doped silicon germanium having a lattice spacing greater than a lattice spacing of the substrate material and phosphorus doped silicon-carbon alloy having a lattice spacing less than the lattice spacing of the substrate material.
9. The method of claim 3 , wherein forming comprises one of forming a sufficient thickness of boron doped silicon germanium to cause a compressive strain in a channel of the substrate between the first facet and the second facet, and forming a sufficient thickness of phosphorus doped silicon-carbon alloy to cause a tensile strain in a channel of the substrate between the first facet and the second facet.