Patent Assignment
Reel/Frame 060392/0594
Assignment of Assignor's Interest
Recorded: 2022-06-06
Pages: 7
Assignor
INTEL CORPORATION
Executed: 2022-06-03
Assignee
DAEDALUS PRIME LLC
51 PONDFIELD ROAD, BRONXVILLE, NEW YORK, 10708
Covered Properties
(51)
Cmos Transistor Junction Regions Formed by a Cvd Etching and Deposition Sequence
Cmos Transistor Junction Regions Formed by a Cvd Etching and Deposition Sequence
Cmos Transistor Junction Regions Formed by a Cvd Etching and Deposition Sequence
Dynamically Allocating a Power Budget Over Multiple Domains of a Processor
Enabling A Non-Core Domain To Control Memory Bandwidth In A Processor
Providing Common Caching Agent For Core And Integrated Input/Output (IO) Module
User Level Control Of Power Management Policies
Method, Apparatus, and System for Energy Efficiency and Energy Conservation Including Power and Performance Workload-Based Balancing Between Multiple Processing Elements
Asymmetric Performance Multicore Architecture with Same Instruction Set Architecture
Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached
Load Balancing and Merging of Tessellation Thread Workloads
Processors Having Virtually Clustered Cores and Cache Slices
Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor
User Level Control of Power Management Policies
Controlling Operating Voltage Of A Processor
Methods and Apparatuses to Form Self-Aligned Caps
Capping Dielectric Structure for Transistor Gates
Method and Device for Secure Communications Over a Network Using a Hardware Security Engine
Assisted Coherent Shared Memory
Dynamically Allocating a Power Budget Over Multiple Domains of a Processor
Enabling A Non-Core Domain To Control Memory Bandwidth In A Processor
Method, Apparatus, and System for Energy Efficiency and Energy Conservation Including Power and Performance Balancing Between Multiple Processing Elements and/or a Communication Bus
Providing Common Caching Agent For Core And Integrated Input/Output (IO) Module
Load Balancing and Merging of Tessellation Thread Workloads
Methods and Apparatuses to Form Self-Aligned Caps
User Level Control Of Power Management Policies
Capping Dielectric Structures for Transistor Gates
Techniques for Integration of Ge-Rich P-Mos Source/Drain
Enabling A Non-Core Domain To Control Memory Bandwidth In A Processor
Controlling Operating Voltage of a Processor
Assisted Coherent Shared Memory
User Level Control Of Power Management Policies
Enabling A Non-Core Domain To Control Memory Bandwidth In A Processor
Asymmetric Performance Multicore Architecture with Same Instruction Set Architecture
Methods and Apparatuses to Form Self-Aligned Caps
Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus
Techniques for Integration of Ge-Rich P-Mos Source/Drain
Processors Having Virtually Clustered Cores and Cache Slices
Processors Having Virtually Clustered Cores and Cache Slices
Processors Having Virtually Clustered Cores and Cache Slices
Controlling Operating Voltage Of A Processor
Asymmetric Performance Multicore Architecture with Same Instruction Set Architecture
Techniques for Integration of Ge-Rich P-Mos Source/Drain
Enabling A Non-Core Domain To Control Memory Bandwidth In A Processor
Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus
Controlling Operating Voltage Of A Processor
Methods and Apparatuses to Form Self-Aligned Caps
Methods and Apparatuses to Form Self-Aligned Caps
Application:
16/908,478 →
Publication:
US 2020/0321282
Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus
Controlling Operating Voltage of a Processor
Application:
17/501,580 →
Controlling Operating Voltage of a Processor
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 4, 2005
From: MURTHY, ANAND; GLASS, GLENN A.; WESTMEYER, ANDREW N.; HATTENDORF, MICHAEL L.
To: INTEL CORPORATION
Reel/Frame 016155/0557 →
Assignment of Assignor's Interest
Sep 7, 2011
From: ANANTHAKRISHNAN, AVINASH N; ROTEM, EFRAIM; RAJWAN, DORON; WEISSMANN, ELIEZER
To: INTEL CORPORATION
Reel/Frame 026863/0663 →
Assignment of Assignor's Interest
Jan 3, 2012
From: ANANTHAKRISHNAN, AVINASH N.; SODHI, INDER M.; ROTEM, EFRAIM; RAJWAN, DORON
To: INTEL CORPORATION
Reel/Frame 027469/0414 →
Assignment of Assignor's Interest
Apr 9, 2012
From: LIU, YEN-CHENG; BLANKENSHIP, ROBERT G.; SANTHANAKRISHNAN, GEEYARPURAM N.; SRINIVASA, GANAPATI N.
To: INTEL CORPORATION
Reel/Frame 028011/0132 →
Assignment of Assignor's Interest
Apr 13, 2012
From: GEORGE, VARGHESE; JAHAGIRDAR, SANJEEV S.; MARR, DEBORAH T.
To: INTEL CORPORATION
Reel/Frame 028046/0420 →
Assignment of Assignor's Interest
Oct 29, 2012
From: LI, YUNJIU; GREEN, MICHAEL
To: INTEL CORPORATION
Reel/Frame 029207/0369 →
Assignment of Assignor's Interest
Dec 13, 2012
From: SISTLA, KRISHNAKANTH V.; SHRALL, JEREMY; GUNTHER, STEPHEN H.; ROTEM, EFRAIM
To: INTEL CORPORATION
Reel/Frame 029462/0303 →
Assignment of Assignor's Interest
Mar 21, 2013
From: WELLS, RYAN D.; FEIT, ITAI; RAJWAN, DORON; SHULMAN, NADAV
To: INTEL CORPORATION
Reel/Frame 030058/0216 →
Assignment of Assignor's Interest
Mar 29, 2013
From: HUM, HERBERT H.; GANESH, BRINDA; VASH, JAMES R.; KUMAR, GANESH
To: INTEL CORPORATION
Reel/Frame 030114/0247 →
Assignment of Assignor's Interest
May 8, 2013
From: SCHLUESSLER, TRAVIS T.; FENGER, RUSSELL J.
To: INTEL CORPORATION
Reel/Frame 030371/0478 →
Assignment of Assignor's Interest
May 10, 2013
From: SCHLUESSLER, TRAVIS T.; FENGER, RUSSELL J.
To: INTEL CORPORATION
Reel/Frame 030391/0110 →
Assignment of Assignor's Interest
Aug 15, 2013
From: BOYANOV, BOYAN; SINGH, KANWAL JIT
To: INTEL CORPORATION
Reel/Frame 031022/0160 →
Corrective Assignment to Correct the Fifth Inventor's Name Previously Recorded at Reel: 027469 Frame: 0414. Assignor(S) Hereby Confirms the Assignment.
Feb 17, 2016
From: ANANTHAKRISHNAN, AVINASH N.; SODHI, INDER M.; ROTEM, EFRAIM; RAJWAN, DORON
To: INTEL CORPORATION
Reel/Frame 037838/0285 →
Assignment of Assignor's Interest
Dec 12, 2025
From: DAEDALUS PRIME LLC
To: MEDIATEK INC.
Reel/Frame 073948/0951 →