Controlling operating voltage of a processor

1. A system on chip (SoC) comprising:

a first unit including a first plurality of cores and at least one cache memory;

a second unit including a second plurality of cores and at least one other cache memory;

a coherent fabric to couple the first unit and the second unit; and

a power controller to receive a first request to increase an operating voltage to be provided to a first core of the first plurality of cores to a second voltage and, responsive to the first request, cause a voltage regulator to increase the operating voltage to an interim voltage, thereafter enable a second core of one of the first plurality of cores and the second plurality of cores to exit an inactive state and enter an active state, and thereafter enable an operating frequency of the first core to be increased.

2. The SoC of claim 1 , wherein the interim voltage is less than the second voltage.

3. The SoC of claim 1 , wherein the power controller is to receive a second request to wake up the second core after the increase of the operating voltage to the interim voltage has occurred.

4. The SoC of claim 1 , wherein the power controller is to cause a multi-step increase to the operating voltage, the multi-step increase including the interim voltage and the second voltage.

5. The SoC of claim 1 , wherein the power controller comprises a microcontroller.

6. The SoC of claim 5 , wherein the microcontroller is to:

receive the first request responsive to a request for the first core to enter into an opportunistic performance state; and

enable the first core to enter into the opportunistic performance state responsive to receipt of an acknowledgement from the voltage regulator that the operating voltage has reached the second voltage.

7. The SoC of claim 5 , wherein the power controller further comprises at least one finite state machine coupled to the microcontroller.

8. The SoC of claim 7 , wherein the at least one finite state machine comprises a preemptible state machine, the preemptible state machine to undergo a transition to an initial state without completion of a prior transition.

9. The SoC of claim 1 , wherein the power controller is to:

receive a first acknowledgement from the voltage regulator that the operating voltage has reached the interim voltage and responsive to the first acknowledgement, cause the voltage regulator to increase the operating voltage to the second voltage; and

receive a second request for the second core to exit the idle state, and to enable the second core to exit the idle state after receipt of the first acknowledgement.

10. The SoC of claim 9 , wherein the power controller is to:

receive a third request for the first core to enter a turbo mode, and to cause the voltage regulator to increase the operating voltage to a third voltage greater than the second voltage; and

enable the first core to enter into the turbo mode responsive to a second acknowledgement from the voltage regulator that the operating voltage has reached the third voltage.

11. The SoC of claim 1 , further comprising a graphics unit coupled to the coherent fabric.

12. The SoC of claim 1 , further comprising an image signal processor coupled to the coherent fabric.

13. The SoC of claim 1 , further comprising a second fabric coupled to the coherent fabric.

14. The SoC of claim 13 , wherein the second fabric comprises a non-coherent fabric.

15. The SoC of claim 1 , further comprising at least one on-chip low dropout regulator comprising the voltage regulator.

16. A method comprising:

receiving, in a power controller of a system on chip (SoC), a performance state change request to increase a performance state of a first core;

communicating an operating voltage increase request to a first voltage regulator coupled to the SoC to request the first voltage regulator to increase an operating voltage provided to the SoC from a first voltage level to an interim voltage level; and

after the operating voltage reaches the interim voltage level, enabling a second core of the SoC to exit from an inactive state to an active state before enabling the first core to effect an operating frequency increase.

17. The method of claim 16 , further comprising receiving a request to wakeup the second core after initiating an update to cause the operating voltage to be updated to a second voltage level, and enabling the second core to wakeup before the operating voltage reaches the second voltage level, the second voltage level greater than the interim voltage level.

18. A system comprising:

a system on chip (SoC) including:

a first unit including a first plurality of cores and at least one cache memory;

a second unit including a second plurality of cores and at least one other cache memory;

one or more graphics processing units;

a power controller to cause an operating voltage to be updated, according to a multi-level operating voltage ramp profile, to a second level sufficient to support at least one core at a turbo mode frequency;

a coherent fabric to couple to the first unit, the second unit and the one or more graphics processing units;

a non-coherent fabric to couple to the coherent fabric; and

one or more devices to couple to the non-coherent fabric;

a voltage regulator coupled to the SoC to provide the operating voltage to the SoC;

wherein the power controller is to send a plurality of requests to the voltage regulator to cause the voltage regulator to update the operating voltage to the second level according to the multi-level operating voltage ramp profile; and

a dynamic random access memory (DRAM) coupled to the SoC.

19. The system of claim 18 , wherein upon completion of a first portion of the multi-level operating voltage ramp profile, the operating voltage is sufficient to support an additional core at a first frequency.