Controlling operating voltage of a processor
In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
1. A processor comprising:
a first domain including a plurality of processing cores; and
a power controller including a first logic to receive a first request to increase an operating voltage provided to a first processing core of the first domain to a second voltage and to increase a frequency of the first processing core, and responsive to the first request to instruct a voltage regulator to increase the operating voltage provided to the first processing core of the first domain to an interim voltage and to thereafter enable a second processing core of the first domain to exit a low power state in which the second processing core is inactive to an active state, and thereafter enable the frequency of the first processing core to be increased.
2. The processor of claim 1 , wherein the power controller includes a microcontroller and a dispatcher engine.
3. The processor of claim 2 , wherein the dispatcher engine comprises a pre-emptible state machine.
4. The processor of claim 3 , wherein the first logic comprises the dispatcher engine.
5. The processor of claim 2 , wherein the dispatcher engine is to receive the first request from the microcontroller responsive to a request for the first processing core to enter a turbo mode.
6. The processor of claim 5 , wherein the dispatcher engine is to enable the first processing core to enter the turbo mode responsive to receipt of an acknowledgement from the voltage regulator that the operating voltage has reached the second voltage.
7. The processor of claim 1 , wherein the first logic is to receive a first acknowledgement from the voltage regulator that the operating voltage has reached the interim voltage, and to instruct the voltage regulator to increase the operating voltage to the second voltage responsive to the first acknowledgement.
8. The processor of claim 7 , wherein the first logic is to receive a second request for the second processing core of the first domain to exit the low power state, and to enable the second processing core to exit the low power state after receipt of the first acknowledgement.
9. The processor of claim 7 , wherein the first logic is to receive a third request for the first processing core to enter a turbo mode, and to instruct the voltage regulator to increase the operating voltage to a third voltage greater than the second voltage.
10. The processor of claim 9 , wherein the first logic is to enable the first processing core to enter the turbo mode responsive to a second acknowledgement from the voltage regulator that the operating voltage has reached the third voltage.
11. The processor of claim 1 , wherein the interim voltage comprises a voltage level sufficient to enable an additional processing core.
12. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving a frequency increase request for a first intellectual property (IP) logic of a processor, the first IP logic comprising a first core of the processor;
causing an operating voltage provided to the processor by a first voltage regulator coupled to the processor to be updated from a first voltage level to an interim voltage level; and
after the operating voltage reaches the interim voltage level, enabling a second IP logic of the processor comprising a second core of the processor to exit from a low power state in which the second IP logic is inactive to an active state before enabling the first IP logic to effect the frequency increase.
13. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises receiving a request to wakeup the second IP logic after initiating an update to cause the operating voltage to be updated to a second voltage level, and enabling the second IP logic to wakeup before the operating voltage reaches the second voltage level.
14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises causing the operating voltage to be updated to a third voltage level greater than the second voltage level.
15. The non-transitory machine-readable medium of claim 14 , wherein the method further comprises after the operating voltage reaches the third voltage level, enabling the first IP logic to enter a turbo mode.
16. The non-transitory machine-readable medium of claim 15 , wherein the method further comprises:
causing the operating voltage to be updated to the interim voltage level, responsive to a request for the first IP logic to exit the turbo mode; and
causing the operating voltage to be updated to the first voltage level, after at least one of the first and second IP logics enters a low power mode.