Techniques for integration of Ge-rich p-MOS source/drain contacts
Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm −3 .
1. A transistor device, comprising:
a substrate having a channel region;
a gate electrode above the channel region; and
source/drain regions adjacent to the channel region, each of the source/drain regions comprising a p-type germanium (Ge)-rich layer in direct contact with a silicon (Si) surface, wherein the p-type Ge-rich layer comprises at least 50% Ge throughout the entire p-type Ge-rich layer.
2. The device of claim 1 , wherein the Si surface in the source/drain regions is a surface of the substrate.
3. The device of claim 1 , wherein the Si surface in the source/drain regions is a surface of a Si cladding layer deposited on a p-type silicon germanium (SiGe) layer.
4. The device of claim 3 , wherein the p-type SiGe layer comprises 30-70% Ge.
5. The device of claim 1 , wherein the p-type Ge-rich layer comprises silicon germanium (SiGe).
6. The device of claim 1 , wherein the p-type Ge-rich layer comprises germanium tin (GeSn) with up to 15% Sn.
7. The device of claim 6 , wherein the p-type Ge-rich layer further comprises up to 5% Si.
8. The device of claim 1 , wherein the p-type Ge-rich layer is boron (B) doped at levels above 1E20 cm −3 .
9. The device of claim 1 , wherein the Si surface is undoped or has doping levels below 1E19 cm −3 .
10. The device of claim 1 , further comprising metal-germanide source/drain contacts.
11. A CMOS device comprising an n-MOS device and the device of claim 1 .
12. The device of claim 1 , wherein the device has a planar, finned, nanowire, or nanoribbon configuration.
13. An integrated circuit comprising the device of claim 1 .
14. The integrated circuit of claim 13 , further comprising additional source/drain regions, wherein the additional source/drain regions lack metal contacts and comprise a silicon germanium (SiGe) layer.
15. A computing system comprising the device of claim 1 .
16. A method for forming a transistor device, the method comprising:
performing shallow trench isolation (STI) on a silicon (Si) substrate having a channel region;
forming a gate stack above the channel region;
depositing a sacrificial silicon germanium (SiGe) layer in source/drain regions adjacent to the channel region;
depositing an insulator material over topography of the gate stack and source/drain regions;
performing source/drain contact trench etch;
etching to remove the sacrificial SiGe layer from the source/drain contact trenches and re-expose a surface of the Si substrate; and
depositing a p-type germanium (Ge)-rich layer in the source/drain contact trenches on the re-exposed surface of the Si substrate, wherein the p-type Ge-rich layer comprises at least 50% Ge throughout the entire p-type Ge-rich layer.
17. The method of claim 16 , wherein the p-type Ge-rich layer is deposited at temperatures of less than 500 degrees C.
18. The method of claim 16 , wherein etching to remove the sacrificial SiGe layer includes using a SiGe etch that is selective to silicon (Si) and insulator materials.
19. The method of claim 16 , wherein etching to remove the sacrificial SiGe layer is a wet etch including water, nitric acid, organic acid, and/or hydrofluoric acid.
20. The method of claim 16 , wherein the sacrificial SiGe layer comprises 15-30% Ge and is undoped.
21. A method for forming a transistor device, the method comprising:
performing shallow trench isolation (STI) on a substrate having a channel region;
forming a gate stack above the channel region;
depositing a p-type silicon germanium (SiGe) layer in source/drain regions adjacent to the channel region;
depositing a silicon (Si) cladding layer on the p-type SiGe layer;
depositing an insulator material over topography of the gate stack and source/drain regions;
performing source/drain contact trench etch; and
depositing a p-type germanium (Ge)-rich layer on the Si cladding layer in the source/drain contact trenches, wherein the p-type Ge-rich layer comprises at least 50% Ge throughout the entire p-type Ge-rich layer.
22. The method of claim 21 , wherein the p-type Ge-rich layer is deposited at temperatures of less than 500 degrees C.
23. The method of claim 21 , further comprising depositing an etch stop layer over topography of the gate stack and source/drain regions prior to depositing the insulator layer, wherein the etch stop layer helps protect the Si cladding layer during source/drain contact trench etch.
24. The method of claim 23 , wherein the etch stop layer is one of a nitride or carbide material.
25. The method of claim 21 , wherein the p-type SiGe layer comprises 30-70% Ge.