Dynamically allocating a power budget over multiple domains of a processor
In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
1. An apparatus, comprising:
a system on an integrated circuit, comprising:
a first entity having a processor including a plurality of processing cores;
a second entity having a graphics engine;
a cache;
an integrated memory controller;
an interface to communicate in accordance with a first communication protocol;
first logic to dynamically allocate a power budget between the processor and the graphics engine based at least in part on a first sharing policy value for the first entity and a second sharing policy value for the second entity; and
second logic to determine a voltage and frequency point for the graphics engine based on a thermal design power (TDP) limit.
2. The apparatus of claim 1 , wherein the first logic comprises a power controller.
3. The apparatus of claim 2 , wherein the power controller to dynamically allocate a power budget between the processor and the graphics engine comprises the power controller to dynamically allocate more of the power budget to the processor than the graphics engine.
4. The apparatus of claim 2 , wherein the power controller to dynamically allocate a power budget between the processor and the graphics engine comprises the power controller to dynamically allocate less of the power budget to the processor than the graphics engine.
5. The apparatus of claim 1 , wherein the first logic and the second logic are included in a power controller, and wherein the second logic is to execute code to determine the voltage and frequency point for the graphics engine based on the TDP limit.
6. The apparatus of claim 1 , wherein the TDP limit is a limit based on a power and thermal calculation.
7. An apparatus, comprising:
an integrated circuit, comprising:
a processor domain including a plurality of processing cores;
a graphics domain having a graphics engine;
a cache;
an integrated memory controller;
a power controller to dynamically allocate a particular portion of a power budget for at least the processor domain and the graphics domain based at least on a first sharing policy value for the processor domain, a second sharing policy value for the graphics domain and a graphics workload, wherein the particular portion of the power budget is to be greater than a second portion to be allocated to the processor domain; and
firmware to determine a voltage and frequency point for the graphics engine based on at least the particular portion of the power budget.
8. The apparatus of claim 7 , wherein the power budget is to be based on a thermal design power (TDP) limit.
9. The apparatus of claim 8 , wherein the integrated circuit further comprises an interface to communicate in accordance with a first communication protocol.
10. A system, comprising:
a display;
an audio I/O;
a chipset;
a keyboard;
a communication device;
a first entity having a processor including a plurality of processing cores;
a second entity having a graphics engine;
a cache;
a memory controller;
first logic to dynamically allocate a power budget between the processor and the graphics engine based at least in part on a first sharing policy value for the first entity and a second sharing policy value for the second entity; and
second logic to determine a voltage and frequency point for the graphics engine based on a thermal design power (TDP) limit.
11. The system of claim 10 , wherein the first logic comprises a power controller.
12. The system of claim 11 , wherein the power controller to dynamically allocate a power budget between the processor and the graphics engine comprises the power controller to dynamically allocate more of the power budget to the processor than the graphics engine.
13. The system of claim 11 , wherein the power controller to dynamically allocate a power budget between the processor and the graphics engine comprises the power controller to dynamically allocate less of the power budget to the processor than the graphics engine.
14. The system of claim 10 , wherein the first logic and the second logic are included in a power controller, and wherein the second logic is configured to execute code to determine the voltage and frequency point for the graphics engine based on the TDP limit.
15. The system of claim 10 , wherein the TDP limit is a limit based on a power and thermal calculation.
16. A non-transitory computer readable medium including code, when executed, to cause a machine to:
dynamically allocate a power budget on an integrated circuit between a processor domain including a plurality of processing cores and a graphics domain including a graphics engine based at least in part on a first sharing policy value for the processor domain and a second sharing policy value for the graphics domain, wherein the integrated circuit includes a cache, an integrated memory controller, and a I/O interface;
determine a voltage and frequency point for the graphics engine based on a thermal design power (TDP) metric; and
adjust the graphics engine to the voltage and frequency point in response to determining the voltage and frequency point.
17. The non-transitory computer readable medium of claim 16 , wherein a power controller is to dynamically allocate the power budget on the integrated circuit.
18. The non-transitory computer readable medium of claim 16 , wherein firmware is to determine the voltage and frequency point.
19. A method comprising
dynamically allocating a power budget on an integrated circuit between a processor domain including a plurality of processing cores and a graphics domain including a graphics engine based at least in part on a first sharing policy value for the processor domain and a second sharing policy value for the graphics domain, wherein the integrated circuit includes a cache, an integrated memory controller, and a I/O interface;
determining a voltage and frequency point for the graphics engine based on a thermal design power (TDP) metric; and
adjusting the graphics engine to the voltage and frequency point in response to determining the voltage and frequency point.
20. The method of claim 19 , wherein a power controller is to dynamically allocate the power budget on the integrated circuit.
21. The method of claim 19 , wherein firmware is to determine the voltage and frequency point.