Capping dielectric structure for transistor gates
The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.
1. A method comprising:
forming a sacrificial non-planar transistor gate over a non-planar transistor fin;
depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin;
forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;
forming a source/drain region;
removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;
forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;
depositing conductive gate material within the gate trench;
removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers;
forming a capping dielectric structure within the recess by high density plasma depositing a dielectric material;
forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and
forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region.
2. The method of claim 1 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon nitride capping dielectric structure.
3. The method of claim 1 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing a silicon carbide capping dielectric structure.
4. The method of claim 1 , wherein high density plasma depositing the capping dielectric structure comprises high density plasma depositing the capping dielectric structure at a temperature between about 300° C. and 600° C.
5. The method of claim 1 , wherein forming a capping dielectric structure comprises:
high density plasma depositing capping dielectric material within the recess; and
removing excess capping dielectric material.
6. The method of claim 1 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material which exposes at least a portion of the source/drain region and at least a portion of one non-planar transistor gate spacer.
7. The method of claim 6 , further comprising forming a source/drain contact to abut the exposed portion of the source/drain region and exposed portion of the non-planar transistor gate spacer.
8. The method of claim 1 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material which exposes at least a portion of the source/drain region and at least a portion of the capping dielectric structure.
9. The method of claim 8 , further comprising forming a source/drain contact abuts the exposed portion of the source/drain region and the exposed portion of the capping dielectric structure.
10. The method of claim 1 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material exposes at least a portion of the source/drain region, at least a portion of the non-planar transistor gate spacer, and at least a portion of the capping dielectric structure.
11. The method of claim 10 , further comprising forming a source/drain contact to abut the exposed portion of the source/drain region, the exposed portion of non-planar gate spacer, and the exposed portion of the capping dielectric structure.