IP Library Granted Patent US 7,650,459
Granted Patent B2
US 7,650,459 · App. 11/644,270 · Granted Jan 19, 2010

High speed interface for non-volatile memory

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Quick Facts
Patent No.
US 7,650,459
App. No.
11/644,270
Granted
Jan 19, 2010
Kind
B2
Abstract

Various embodiments of the invention connect multiple non-volatile memory controllers in a daisy chain manner, so the multiple memory devices may be accessed from a common host controller. Data and control signals may be daisy-chained in this way, so that many memory devices may be connected together, while not increasing the loading on individual signals lines. Transfer with the various memory devices may be interleaved, so that the relatively slow times of the memory devices doesn't slow down the overall throughout of the memory stem.

Claims (29)

1. An apparatus, comprising

a controller to control operations of first and second non-volatile memory devices connected in a daisy-chain manner, the controller to:

issue a first command to the first device to transfer first data to the controller;

issue a second command to the second device, subsequent to said issuing the first command, to transfer second data to the controller;

receive a first part of the first data from the first device, subsequent to said issuing the second command;

receive a first part of the second data from the second device, subsequent to said receiving the first part of the first data;

receive a second part of the first data from the first device, subsequent to said receiving the first part of the second data; and

receive a second part of the second data from the second device, subsequent to said receiving the second part of the first data.

2. The apparatus of claim 1 , further comprising assembling the first and second parts of the first data and the first and second parts of the second data into a single block of data, subsequent to issuing read commands as the first and second commands.

3. The apparatus of claim 1 , further comprising separating a single block of data into the first and second parts of the first and second data, prior to issuing write commands as the first and second commands.

4. A method, comprising:

issuing a first command from a controller to a first memory device to transfer first data to the controller;

issuing a second command from the controller to a second device, subsequent to said issuing the first command, to transfer second data to the controller;

receiving, by the controller, a first part of the first data from the first device, subsequent to said issuing the second command;

receiving, by the controller, a first part of the second data from the second device, subsequent to said receiving the first part of the first data;

receiving, by the controller, a second part of the first data from the first device, subsequent to said receiving the first part of the second data; and

receiving, by the controller, a second part of the second data from the second device, subsequent to said receiving the second part of the first data.

5. The method of claim 4 , further comprising assembling, in the controller, the first and second parts of the first data and the first and second parts of the second data into a single block of data, subsequent to issuing read commands as the first and second commands.

6. The method of claim 4 , further comprising separating, in the controller, a single block of data into the first and second parts of the first and second data, prior to issuing write commands as the first and second commands.

7. An article comprising

a tangible machine-readable medium that contains instructions, which when executed by one or more processors result in performing operations comprising:

issuing a first command from a controller to a first memory device to transfer first data to the controller;

issuing a second command from the controller to a second device, subsequent to said issuing the first command, to transfer second data to the controller;

receiving, by the controller, a first part of the first data from the first device, subsequent to said issuing the second command;

receiving, by the controller, a first part of the second data from the second device, subsequent to said receiving the first part of the first data;

receiving, by the controller, a second part of the first data from the first device, subsequent to said receiving the first part of the second data; and

receiving, by the controller, a second part of the second data from the second device, subsequent to said receiving the second part of the first data.

8. The article of claim 7 , wherein the operations further comprise assembling, in the controller, the first and second parts of the first data and the first and second parts of the second data into a single block of data, subsequent to issuing read commands as the first and second commands.

9. The article of claim 7 , wherein the operations further comprise separating, in the controller, a single block of data into the first and second parts of the first and second data, prior to issuing write commands as the first and second commands.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062437/0329 →
CHANGE OF NAME Recorded Sep 28, 2009
From: EILERT, SEAN S; ROZMAN, RODNEY R
To: INTEL CORPORATION
Reel/Frame 023293/0848 →