Power saving in NAND flash memory
View Patent ↗Some embodiments of the invention may use a single control line signal as both a wake up signal and as an indicator of a device selection command. In a command-based protocol on a non-volatile memory bus, a host memory controller may assert a signal on a control line to bring all the memory devices on the bus into an operational mode, while concurrently placing a device selection command on the input/output lines. The memory device selected by the selection command may remain operational to perform a sequence of operations as directed by the host controller. The remaining (non-selected) memory devices may return to a sleep mode until a new signal on the control line is received, indicating a new selection command.
1. A non-volatile memory device, comprising:
a plurality of input/output (I/O) signal pins for coupling to a bus and to receive a communications sequence comprising I/O signals from a bus;
a control signal pin for coupling to the bus and to receive a control signal from the bus; and
circuitry to:
transition the non-volatile memory device from a non-operational sleep mode to an operational mode upon assertion of the control signal, the non-volatile memory device to further include a powered-off mode;
determine whether the communications sequence identifies the non-volatile memory device;
in response to determining the communications sequence does not identify the first non-volatile memory device, return the non-volatile memory device to the non-operational sleep mode upon deassertion of the signal on the control pin; and
in response to determining the communications sequence does identify the first non-volatile memory device, remain in the operational mode and perform an operation indicated by the communications sequence.
2. The non-volatile memory device of claim 1 , wherein the non-volatile memory device comprises a flash memory device.
3. The non-volatile memory device of claim 2 , wherein the flash memory device comprises a NAND flash memory device.
4. The non-volatile memory device of claim 1 , further comprising a clock signal pin to receive a clock signal to latch the communications sequence on the I/O pins.
5. A method, comprising:
receiving an asserted control signal and a control sequence on a control signal and a plurality of input/output (I/O) signal pins included on a non-volatile memory device from a host controller via a bus communicatively coupling the non-volatile memory device and the host controller;
changing an operational mode of the non-volatile memory device from a non-operational sleep mode to an operational mode in response to receiving the control signal, the memory device further having a powered-off mode;
in response to changing the non-volatile memory device to the operational mode, determining whether the communications sequence identifies the non-volatile memory device during the control signal;
in response to determining the communications sequence does not identify the non-volatile memory device, returning the non-volatile memory device to the non-operational sleep mode upon deassertion of the control signal; and
in response to determining the communication sequence does identify the non-volatile memory device, remaining in the operational mode after deassertion of the control signal and performing an operation indicated by the communications sequence.
6. The method of claim 5 , further comprising returning to the non-operational low power mode subsequent to performing the operation indicated by the control sequence.
7. The method of claim 5 , wherein the operation indicated by the communications sequence comprises either a read data operation or a write data operation.
8. A system comprising:
a first and a second non-volatile memory device, each device having a set of input/output (I/O) signal pins, a control signal pin, and a plurality device states comprising a powered-off mode, a non-operational sleep mode and an operational mode, the first non-volatile memory device separately selectable from the second non-volatile memory device;
a host controller coupled to the first and the second non-volatile memory devices through a bus connected to the I/O signal pins and the control signal pins of the devices, the host controller to assert a signal on the control signal pin to cause the first and second non-volatile memory devices to transition from the sleep mode to the operational mode, and to assert signals on the I/O pins comprising a communications sequence identifying the first non-volatile memory device;
wherein the first non-volatile memory device is to determine that the communications sequence from the host controller identifies the first non-volatile memory device and to remain in the operational mode after deassertion of the signal on the control signal pin to perform an operation further identified by the communications sequence; and
wherein the second non-volatile memory device is to determine that the communications sequence from the host controller does not identify the second non-volatile memory device and to return to the sleep mode after deassertion of the signal on the control signal pin.
9. The system of claim 8 , wherein the host controller is contained in a different integrated circuit than the first and second non-volatile memory devices.
10. The system of claim 8 , wherein the first and second non-volatile memory devices further comprise a clock pin to receive a clock signal to clock the signals on the I/O pins.
11. The system of claim 8 , wherein the first and the second non-volatile memory devices are included in separate integrated circuits.
12. The system of claim 8 , wherein the first and the second non-volatile memory devices are included in the same integrated circuit.
13. The method of claim 5 , wherein the non-volatile memory device comprises a flash memory device.
14. The method of claim 13 , wherein the flash memory device comprises a NAND flash memory device.