Aiding synchronization between master and slave transceivers
View Patent ↗An apparatus and method of aiding synchronization between a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver transmitting data signals that are received by the slave transceiver. The slave transceiver locks a slave clock to the data signals with a slave phase-locked loop. The slave transceiver transmits slave clock information to the master transceiver.
1. A method of aiding synchronization between a master transceiver and a slave transceiver, comprising:
the master transceiver transmitting data signals that are received by the slave transceiver;
the slave transceiver locking a slave clock to the data signals with a slave phase-locked loop;
the slave transceiver transmitting slave clock information to the master transceiver, wherein the slave clock information comprises an indicator of whether the slave clock is locked to the data signals transmitted by the master transceiver, and wherein the slave clock is designated as locked if data signals transmitted between the master transceiver and the slave transceiver have a signal quality above a predetermined threshold.
2. The method of claim 1 , wherein the data signals include training signals.
3. The method of claim 1 , wherein the indicator is a bit of an Info-field of a 10 GBase-T protocol.
4. The method of claim 1 , wherein the slave clock information comprises at least one indicator of transmission processes of the master transceiver that degrade phase-lock, causing data errors in the data signals
degrade the phase-lock to below an acceptable level causing an unacceptable rate of data error in the data signals.
5. The method of claim 4 , wherein the transmission processes comprise at least one of the master transceiver changing power back-off, the master transceiver changing from half-duplex transmission to full-duplex transmission, the master transceiver enabling THP.
6. The method of claim 5 , wherein the slave clock information comprises at least one indicator of time periods, wherein the time periods include at least one of the slave transceiver adjusting its phase-locked loop bandwidth, the slave transceiver changing transmission from half-duplex to full-duplex, the slave transceiver changing its power back-off, the slave transceiver enabling THP.
7. The method of claim 1 , wherein the slave clock information comprises processing recommendations to the master transceiver.
8. The method of claim 7 , wherein the processing recommendations comprise requests to the master transceiver when to suppress certain master transceiver processing that can cause the slave clock to lose phase-lock with the data signals transmitted by the master transceiver.
9. The method of claim 7 , wherein the master transceiver suppresses select processing activities based on the processing recommendations that cause the master adaptive processing to diverge.
10. The method of claim 9 , wherein the master transceiver slows equalizer and canceller coefficient adaptations based on the processing recommendations.
11. A method of adaptively adjusting processing of a master transceiver, comprising:
the master transceiver transmitting data signals to a link partner transceiver;
master transceiver receiving slave clock information from the link partner transceiver;
the master transceiver adaptively adjusting processing according to the slave clock information provided by the link partner transceiver;
wherein the master transceiver slows selective types of processing of transmission signals received from the link partner because a quality of the phase-lock of the slave clock falls below a threshold.
12. The method of claim 11 , wherein adaptively adjusting the processing comprises suppressing processing that cause the link partner to lose phase-lock with the data signals.
13. The method of claim 11 , further comprising:
the transceiver transmitting training signals to the link partner to aid the link partner in improving phase-lock with the data signals of the transceiver.
14. A method of maintaining phase-lock with a master transceiver comprising:
a slave transceiver phase-locking a slave clock to data signals received from a master transceiver;
the slave transceiver providing the master transceiver with slave clock information, wherein the slave clock information comprises an indicator of whether the slave clock is locked to the data signals transmitted by the master transceiver, and wherein the slave clock is designated as locked if data signals transmitted between the master transceiver and the slave transceiver have a signal quality above a predetermined threshold.
15. The method of claim 14 , wherein the indicator is a bit of an Info-field of a 10GBase-T protocol.
16. The method of claim 14 , wherein the slave clock information comprises at least one indicator of transmission processes of the master transceiver that degrade phase-lock, causing data errors in the data signals.
17. The method of claim 14 , wherein the slave clock information comprises at least one indicator of time periods, wherein the time periods include at least one of the slave transceiver adjusting its phase-locked loop bandwidth, the slave transceiver changing transmission from half-duplex to full-duplex, the slave transceiver changing its power back-off, the slave transceiver enabling THP.
18. The method of claim 14 , wherein the slave clock information comprises processing recommendations to the master transceiver.
19. The method of claim 14 , further comprising the slave transceiver requesting the master transceiver to transmit training signals if a quality of the phase-lock of the slave clock falls below a threshold.
20. The method of claim 14 , wherein the slave clock is designated as locked if data transmitted between the master transceiver and the slave transceiver has an estimated signal quality below a predetermined threshold.