Method for manufacturing bipolar transistor
View Patent ↗A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the semiconductor substrate; forming an emitter electrode pattern on the third well region, and forming a collector electrode pattern on the second well region; forming spacers at sidewalls of the emitter and collector electrode patterns; performing a diffusion process to form an emitter region of a first conductivity on the third well region and to form a collector region of a first conductivity on the second well region; implanting ions of a second conductivity in the third well region to form a base region; and removing the emitter electrode and collector region patterns.
1. A method for manufacturing a bipolar transistor comprising:
forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity;
implanting ions of a second conductivity in the first well to form a third well;
depositing and patterning a conductive layer on the third well region;
forming an emitter electrode pattern on the third well region and a collector electrode pattern on the second well region;
forming spacers on sidewalls of the emitter and collector electrode patterns;
performing a diffusion process on the semiconductor substrate to form an emitter region of a first conductivity on the third well region and to form a collector region of a first conductivity on the second well region;
implanting ions of a second conductivity in the third well region to form a base region; and
removing the emitter electrode pattern and the collector region pattern.
2. The method according to claim 1 , further comprising forming a dielectric layer on the substrate to form a contact hole exposing the emitter region, the base region, and the collector region, after the emitter electrode pattern and the collector region pattern have been removed; and
depositing a conductive layer in the contact hole to form contact plugs in contact with the emitter region, the base region, and the collector region.
3. The method according to claim 1 , wherein the conductive layer comprises a polysilicon layer containing a first conductivity type dopant.
4. The method according to claim 3 , wherein the first conductivity is n-type, the second conductivity is p-type.
5. The method according to claim 3 , wherein the first conductivity is n-type, the second conductivity is p-type.
6. The method according to claim 1 , further comprising implanting n+ ions in the conductive layer.