Capacitor and manufacturing method thereof
View Patent ↗The disclosure concerns a capacitor including a trench; an insulation layer; a first polysilicon layer; a first patterned dielectric layer; a second polysilicon layer patterned into a plurality of vertical bars in the trench; a second dielectric layer along surfaces of the first dielectric layer and the second patterned polysilicon layer; and a third polysilicon layer on the second dielectric layer.
1. A method of manufacturing a capacitor, comprising:
forming a trench by etching part of a silicon substrate;
depositing in turn an insulation layer, a first polysilicon layer, and a first dielectric layer on the silicon substrate;
patterning the first dielectric layer to expose a portion of the first polysilicon layer and in the exposed portion of the first polysilicon layer;
depositing a second polysilicon layer on the first dielectric layer and in the exposed portion of the first polysilicon layer;
forming a plurality of separated vertical bars in the trench by patterning the second polysilicon layer;
depositing a conformal second dielectric layer along surfaces of the first dielectric layer and the plurality of separated vertical bars of the second polysilicon layer; and
depositing and patterning a third polysilicon layer on the second dielectric layer.
2. The method as claimed in claim 1 , further comprising:
forming contacts connected to the first polysilicon layer and the third polysilicon layer, respectively.
3. The method of claim 1 , wherein patterning the second polysilicon layer forms at least two vertical bars.
4. The method of claim 1 , wherein patterning the second polysilicon layer forms at least three vertical bars.
5. The method of claim 1 , wherein the first and second dielectric layers comprise SiO 2 or Si 3 N 4 .
6. The method of claim 1 , wherein the first and second dielectric layers comprise different materials.
7. The method of claim 1 , wherein etching comprises chemical etching, sputter etching, plasma etching, ion milling, reactive ion etching, or a combination thereof.
8. The method of claim 1 , wherein a height of the separated vertical bars extends above the trench.
9. The method of claim 1 , further comprising forming a field oxide layer on the silicon substrate before forming the trench.
10. The method of claim 1 , comprising etching the trench to a depth of from 4,000 to 8,000 Å.
11. The method of claim 2 , further comprising forming an inter-layer insulation layer on the third polysilicon layer and portions of the second dielectric layer.
12. The method of claim 11 , wherein the contacts are formed in the inter-layer insulation layer.
13. The method of claim 12 , further comprising forming metal wires on the inter-layer insulation layer, wherein the metal wires are connected to the first polysilicon layer and the third polysilicon layer through the contacts.
14. The method of claim 2 , wherein the contacts comprise tungsten, doped polysilicon, or copper.
15. The method of claim 2 , wherein forming the contacts comprises forming a barrier liner layer.
16. The method of claim 15 , wherein the barrier liner layer comprises TiN or TaN.
17. The method of claim 2 , wherein the contacts are formed with an adhesive.
18. The method of claim 17 , wherein the adhesive comprises Ti or Ta.