IP Library Granted Patent US 7,488,649
Granted Patent B2
US 7,488,649 · App. 11/645,739 · Granted Feb 10, 2009

Method of manufacturing split gate type non-volatile memory device

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Quick Facts
Patent No.
US 7,488,649
App. No.
11/645,739
Granted
Feb 10, 2009
Kind
B2
Abstract

A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the active region; forming a second conductive film on top of the first conductive film patterns and a remainder of the active region; etchbacking the entire surface of the second conductive film to planarize a top of the second conductive film formed between the first conductive film patterns; forming a photoresist pattern, with an opening corresponding to the active region between the first conductive film patterns, on the second conductive film; and forming a pair of split gates each having one of the first conductive film patterns and a second conductive film pattern formed by patterning the second conductive film using the photoresist pattern as an etching mask.

Claims (27)

1. A method of manufacturing a split gate type non-volatile memory device, comprising the steps of:

defining an active region on a semiconductor substrate;

forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the active region;

forming a second conductive film on top of the first conductive film patterns and the active region outside the first conductive film patterns;

etchbacking the entire surface of the second conductive film to planarize a top of the second conductive film formed between the first conductive film patterns;

forming a photoresist pattern, with an opening corresponding to the active region between the first conductive film patterns, on the second conductive film; and

forming a pair of split gates each having one of the first conductive film patterns and a second conductive film pattern formed by patterning the second conductive film using the photoresist pattern as an etching mask.

2. The method of claim 1 , wherein the step of forming the first conductive film patterns comprises the steps of:

forming the electric charge storage layer and a first conductive film on the active region of the substrate; and

sequentially patterning the first conductive film and the electric charge storage layer and to form the first conductive film patterns facing each other.

3. The method of claim 2 , further comprising the step of forming a capping insulation film on the first conductive film, wherein the sequentially patterning step sequentially patterning and the electric charge storage layer and the capping insulation film, the first conductive film.

4. The method of claim 1 , further comprising the steps of:

forming sidewall insulation film on each sidewall of the first conductive film patterns before the step of forming the second conductive film; and

forming a gate insulation film on the active region at both sides of the first conductive film patterns.

5. The method of claim 1 , wherein the second conductive film is formed with a groove between the first conductive film patterns and the deepest portion of the groove is still higher than a top of each of the first conductive film patterns.

6. The method of claim 5 , wherein the step of etchbacking the second conductive film is performed until the groove is completely removed.

7. The method of claim 5 , wherein the step of etch-backing the second conductive film is performed until the groove is substantially removed.

8. The method of claim 3 , wherein the second conductive film is formed with a groove between the first conductive film patterns, and the deepest portion of the groove is still higher than a top of the capping insulation film on each of the first conductive film patterns.

9. The method of claim 8 , wherein the step of etch-backing the second conductive film is performed until the groove is completely removed.

10. The method of claim 8 , wherein the step of etch-backing the second conductive film is performed until the groove is substantially removed.

11. A method of manufacturing a split gate type non-volatile memory device, comprising the steps of defining an active region on a semiconductor substrate;

forming a pair of first conductive film patterns facing each other on the active region;

forming a second conductive film on top of, at least, the first conductive film patterns, wherein the second conductive film is formed with a groove between the first conductive film patterns, and wherein the deepest portion of the groove is still higher than a top of each of the first conductive film patterns;

planarizing a top surface of said second conductive film to minimize a depth of said groove; and

patterning the second conductive film to form on each of the first conductive film patterns a second conductive film pattern, thereby obtaining a pair of split gates.

12. The method of claim 11 , further comprising the step of forming a capping insulation film on each of the first conductive film patterns prior to the step of forming the second conductive film;

wherein the second conductive film is formed on top of the capping insulation film with the groove located between the first conductive film patterns, and wherein the deepest portion of the groove is still higher than a top of the capping insulation film on each of the first conductive film patterns.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041374/0275 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →