NOR-type flash memory cell array and method for manufacturing the same
View Patent ↗Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in the semiconductor substrate, separated from each other by the isolation layers such that the common source areas connect memory cells adjacent to each other in a bit line direction, a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction, an insulating spacer along a first sidewall of the common source line, a gate at a second sidewall of the insulating spacer including a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode, and a drain area in the semiconductor substrate on an opposite side of the gate from the common source area.
1. A method for manufacturing a non-volatile memory cell array, the method comprising the steps of:
(a) forming a plurality of isolation layers a predetermined distance apart from each other and parallel to each other, on a semiconductor substrate;
(b) forming a plurality of lines orthogonal to the isolation layers and a predetermined distance apart from each other, in which the lines include a tunnel oxide layer, a first electrode layer, an inter-electrode dielectric layer, and a first capping layer;
(c) forming an insulating spacer on a sidewall of each line;
(d) forming a source area by implanting a first dopant into an upper part of the semiconductor substrate between the lines;
(e) selectively removing the first capping layer from the lines;
(f) forming a common source line on the source area between neighboring insulating spacers while forming a pair of second electrode layers a predetermined distance apart from each other on the inter-electrode dielectric layers;
(g) forming a plurality of gates opposite to each other by removing a portion of the line exposed between the second electrode layers; and
(h) forming a drain area by implanting a second dopant into an upper part of the semiconductor substrate between the gates.
2. The method as claimed in claim 1 , wherein step (b) includes the sub-steps of:
(b1) sequentially forming the tunnel oxide layer and the first electrode layer on an entire surface of the semiconductor substrate;
(b2) removing a portion of the electrode layer on the isolation layer;
(b3) sequentially forming the inter-electrode dielectric layer and the first capping layer on an entire surface of the semiconductor substrate including the isolation layer and the first electrode layer; and
(b4) removing a predetermined width of the tunnel oxide layer, the first electrode layer, the inter-electrode dielectric layer, and the first capping layer in a direction vertical to the isolation layer.
3. The method as claimed in claim 2 , wherein, in step (b4), the first electrode layer comprises a plurality of patterned structures spaced from each other by a predetermined distance.
4. The method as claimed in claim 2 , further comprising a step of implanting dopants into the first capping layer prior to step (b4).
5. The method as claimed in claim 1 , wherein step (f) includes the sub-steps of:
(f1) depositing a conductive material on the lines and between the neighboring insulating spacers; and
(f2) simultaneously forming the common source line and the second electrode layer by performing an etch back process with respect to the conductive material.
6. The method as claimed in claim 1 , wherein the common source line is electrically separated from the second electrode layer by the insulating spacer.
7. The method as claimed in claim 5 , wherein, in step (f2), the etch back process is performed until a portion of the insulating spacer is exposed.
8. The method as claimed in claim 1 , wherein the step (g) includes:
(g1) forming a second capping layer on the second electrode layer and the common source line; and
(g2) removing a portion of the inter-electrode dielectric layer and the first electrode layer between a pair of second electrode layers.
9. The method as claimed in claim 1 , further comprising a step of forming a sidewall insulating layer on sidewalls of the gates before performing the step (h).