I/O cell capable of finely controlling drive strength

1. An I/O cell for providing an output pad with an output signal comprising:

a first drive circuit for providing the output pad with an output signal having a drive strength which is equal to a drive strength required by a basic PMOS transistor or a basic NMOS transistor, the first drive circuit further operating as an ESD protection circuit to protect the output pad from any errant electrostatic signal input thereto;

at least one second drive circuit connected between an output of the first drive circuit and the output pad, the second drive circuit operating as an ESD protection circuit to further protect the output pad from any errant electrostatic signal input thereto, wherein the second drive circuit includes:

a PMOS transistor having a first pad, and

an NMOS transistor having a second pad;

a voltage generator for generating VNV and VPG voltages and having a voltage divider connected between a power supply voltage and a ground voltage, wherein the voltage generator includes a switching device:

for selectively connecting an output of the voltage divider to a VNV voltage terminal, and

for selectively connecting the output of the voltage divider to a VPG voltage terminal; and

a second drive stage connected between the VNV voltage terminal and a ground voltage terminal, the second drive stage having an input receiving the input signal of the I/O cell and an output connected to the gate of the NMOS transistor of the second drive circuit.

2. The I/O cell according to claim 1 , wherein the first drive circuit includes a pull-up transistor and a pull-down transistor connected in series between the power supply voltage and the ground voltage, wherein gate inputs of the pull-up and pull-down transistors include a signal ranging from the power supply voltage to the ground voltage.

3. The I/O cell according to claim 1 , wherein the PMOS transistor in the second drive circuit has a source connected to the power supply voltage and a drain connected to the output pad.

4. The I/O cell according to claim 1 , wherein the NMOS transistor in the second drive circuit has a source connected to the ground voltage and a drain connected to the output pad.

5. The I/O cell according to claim 1 , wherein the switching device selectively connects the output of the voltage divider to the VNV voltage terminal and the VPG voltage terminal according to a program signal.

6. An I/O cell for providing an output pad with an output signal comprising:

a first drive circuit for providing the output pad with an output signal having a drive strength which is equal to a drive strength required by a basic PMOS transistor or a basic NMOS transistor, the first drive circuit further operating as an ESD protection circuit to protect the output pad from any errant electrostatic signal input thereto;

at least one second drive circuit connected between an output of the first drive circuit and the output pad, the second drive circuit operating as an ESD protection circuit to further protect the output pad from any errant electrostatic signal input thereto, wherein the second drive circuit includes:

a PMOS transistor having a first pad, and

a NMOS transistor having a second pad;

a voltage generator for generating VNV voltage and VPG voltage and having a voltage divider connected between a power supply voltage and a around voltage, wherein the voltage generator includes a switching device:

for selectively connecting an output of the voltage divider to a VNV voltage terminal, and

for selectively connecting the output of the voltage divider to a VPG voltage terminal;

a second drive stage connected between the VNV voltage terminal and a ground voltage terminal, the second drive stage having an input receiving the input signal of the I/O cell and an output connected to the gate of the NMOS transistor of the second drive circuit; and

a third drive stage connected between a power supply voltage terminal and the VPG voltage terminal, whose input signal is the input signal of the I/O cell and the output is connected to the gate of the PMOS transistor of the second drive circuit.

7. The I/O cell according to claim 1 , wherein the at least one second drive circuit comprises two or more second drive circuits.

8. The I/O cell according to claim 1 , further comprising a third drive stage connected between a power supply voltage terminal and the VPG voltage terminal, the third drive stage having an input receiving the input signal of the I/O cell and an output connected to the gate of the PMOS transistor of the second drive circuit.