IP Library Granted Patent US 8,037,466
Granted Patent B2
US 8,037,466 · App. 11/648,334 · Granted Oct 11, 2011

Method and apparatus for merging critical sections

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,037,466
App. No.
11/648,334
Granted
Oct 11, 2011
Kind
B2
Abstract

Critical sections used for multiple threads in a parallel program to access shared resource may be selected to merge with each other to reduce the number of signals/tokens used to create critical sections. Critical section merge may be based on a summarized dependence graph which is obtained from an instruction level dependence graph constructed based on a result of critical section minimization.

Claims (27)

1. A computer-implemented method for compiling code, comprising:

identifying critical sections in the code;

minimizing the identified critical sections;

constructing an instruction dependence graph of instructions in the code;

generating a summarized dependence graph based on the instruction dependence graph; and

merging at least two of the critical sections based on the summarized dependence graph;

wherein the summarized dependence graph includes only instructions for resource accesses and instructions that start and release the critical sections; and

wherein minimizing the critical sections comprises using multiple threads to hide resource access latencies and using computations out of a critical section to hide resource access latency original in the critical section.

2. The method of claim 1 , further comprising determining data dependence and control dependence of instructions in the code based on the critical section minimization.

3. The method of claim 1 , wherein generating the summarized dependence graph comprises building a relative closure based on the instruction dependence graph.

4. The method of claim 1 , wherein merging at least two of the critical sections comprises merging any two conjoint critical sections in the summarized dependence graph.

5. The method of claim 1 , wherein merging at least two of the critical sections comprises merging a first critical section and a second critical section if there is no resource access instructions between the beginning instruction of the first critical section and the ending instruction of the second critical section or between the beginning instruction of the second critical section and the ending instruction of the first critical section in the summarized dependence graph.

6. The method of claim 1 , further comprising applying a latency sensitive optimization approach to hide resource access latency to the code.

7. The method of claim 1 , wherein a critical section comprises code that may be executed by only one thread at a time.

8. The method of claim 1 , wherein a critical section comprises code that may be executed by only one processor at a time.

9. The method of claim 1 , wherein minimizing the identified critical sections comprises moving a wait instruction from inside a first critical section to outside the first critical section.

10. An article comprising a machine-readable medium that contains instructions, which when executed by a processing platform, cause said processing platform to perform operations for compiling code, the operations including:

identifying critical sections in the code;

minimizing the identified critical sections;

constructing an instruction dependence graph of instructions in the code;

generating a summarized dependence graph based on the instruction dependence graph; and

merging at least two of the critical sections based on the summarized dependence graph;

wherein the summarized dependence graph includes only instructions for resource accesses and instructions that start and release the critical sections; and

wherein minimizing the critical sections comprises using multiple threads to hide resource access latencies and using computations out of a critical section to hide resource access latency original in the critical section.

11. The article of claim 10 , wherein the operations further comprise: constructing the instruction dependence graph of instructions in the code based on the critical section minimization.

12. The article of claim 11 , wherein merging at least two of the critical sections comprises merging any two conjoint critical sections in the summarized dependence graph.

13. The article of claim 11 , wherein merging at least two of the critical sections comprises merging a first critical section and a second critical section if there is no resource access instructions between the beginning instruction of the first critical section and the ending instruction of the second critical section or between the beginning instruction of the second critical section and the ending instruction of the first critical section in the summarized dependence graph.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2008
From: GUO, XIAFENG; DAI, JINQUAN; LI, LONG
To: INTEL CORPORATION
Reel/Frame 020675/0187 →
Continuity (1)
Related Publication 20080163181A1 · Jul 3, 2008