Wafer level package with die receiving through-hole and method of the same
View Patent ↗The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.
1. A structure of semiconductor device package comprising:
a substrate with a die receiving through hole and contact metal pads;
a base attached on a lower surface of said substrate;
a die disposed within said die receiving through hole and attached on said base;
an elastic core paste material filling a space (gap) between the die edge and sidewall of through hole of said substrate
a dielectric layer formed on said die and said substrate;
a re-distribution layer (RDL) formed on said dielectric layer and coupled to said die;
a protection layer formed over said RDL; and
pluralities of terminal pads formed on said protection layer and coupled to said RDL.
2. The structure of claim 1 , further comprising conductive bumps coupled to said pluralities of terminal pads.
3. The structure of claim 1 , wherein said RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.
4. The structure of claim 1 , wherein the material of said substrate includes epoxy type FR5 or FR4.
5. The structure of claim 1 , wherein the material of said substrate includes CCL (copper clad laminate), BT, silicon, PCB (print circuit board) material, glass or ceramic.
6. The structure of claim 1 , wherein the material of said substrate includes alloy or metal.
7. The structure of claim 1 , further includes a cover layer formed under said base.
8. The structure of claim 1 , wherein the material of said dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based layer, a siloxane polymer (SINR) layer, a polyimides (PI) layer or silicone resin layer.
9. The structure of claim 1 , wherein the material of said base includes Alloy42 (42% Ni-58% Fe), silicon, glass, ceramic or Kovar (29% Ni-17% Co-54% Fe).