Scan flip-flop circuit and semiconductor integrated circuit device

1. A scan flip-flop circuit comprising:

a latch section that includes a master part and a slave part that captures an output of said master part;

a hold section with a scan control section that captures an inner state of said latch section responsive to a control signal, and a slave latch section that captures and holds an output state of said scan control section;

a first output node that outputs a first output signal based on said output state; and

a second output node that outputs a second output signal based on said inner state.

2. The scan flip-flop circuit according to claim 1 , wherein said latch section receives first and second input signals and sets said inner state based on said first and second input signals.

3. The scan flip-flop circuit according to claim 2 , wherein said latch section includes:

a first latch section that captures and holds said first and second input signals; and

a second latch section that captures and holds an output of said first latch section.

4. The scan flip-flop circuit according to claim 3 , wherein said first latch section captures said first input signal, responsive to a first clock signal, and captures said second input signal, responsive to a second clock signal.

5. The scan flip-flop circuit according to claim 4 , wherein said second latch section captures and holds an output of said first latch section responsive to said first clock signal and a third clock signal.

6. A semiconductor integrated circuit device including the scan flip-flop circuit as set forth in claim 1 .

7. A scan flip-flop circuit comprising:

a master part that captures a first input signal supplied to a first terminal, responsive to a first clock signal, to set an inner state thereof and that captures a second input signal supplied to a second terminal, responsive to a second clock signal, to set said inner state;

a slave part that captures and holds an output of said master part, responsive to said first and third clock signals;

a hold section that captures and holds an output of said slave part, responsive to a control signal, said hold section having a scan control section that captures said inner state of said latch section and a slave latch section that captures and holds an output state of said scan control section;

a first output node that outputs a first output signal based on said output state; and

a second output node that outputs a second output signal based on said inner state.

8. A semiconductor integrated circuit device including the scan flip-flop circuit as set forth in claim 7 .

9. A scan flip-flop circuit comprising:

a master part that captures a first input signal supplied to a first terminal, responsive to a first clock signal, to set an inner state thereof and that captures a second input signal supplied to a second terminal, responsive to a second clock signal, to set said inner state;

a slave part that captures and holds an output of said master part, responsive to said first and third clock signals; and

a hold section that captures and holds an output of said slave part, responsive to a control signal,

wherein said master part includes:

a first clock control section that captures said first input signal, supplied to said first terminal, responsive to said first clock signal;

a first scan control section that captures said second input signal, supplied to said second terminal, responsive to said second clock signal; and

a master latch section that captures and holds an output of said first clock control section and an output of said first scan control section;

wherein said slave part includes:

a second clock control section that captures an output of said master latch section, responsive to said first clock signal;

a second scan control section that captures an output of said master latch section, responsive to said third clock signal;

a slave latch section that captures and holds an output of said second clock control section and an output of said second scan control section; and

a third scan control section that feeds back an output of said slave latch section to an input of said second clock control section, responsive to said third clock signal;

said slave part outputting a first output signal;

and wherein said hold section includes:

a fourth scan control section that captures an output of said slave latch section responsive to said control signal; and

a second slave latch section that captures and holds an output of said fourth scan control section;

said hold section outputting a second output signal.