Memory including two access devices per phase change element

1. A memory comprising:

a bit line;

a phase change element, a first side of the phase change element coupled to the bit line;

a first access device coupled to a second side of the phase change element;

a second access device coupled to the second side of the phase change element; and

a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.

2. The memory of claim 1 , wherein the first access device comprises a first transistor and the second access device comprises a second transistor.

3. The memory of claim 2 , wherein the first transistor is matched to the second transistor.

4. The memory of claim 2 , further comprising:

a first word line coupled to a gate of the first transistor; and

a second word line coupled to a gate of the second transistor.

5. The memory of claim 4 , wherein the circuit selects the first transistor by applying a first pulse having a first duration to the first word line and selects the second transistor by applying a second pulse having a second duration to the second word line, wherein the circuit programs the phase change element to one of multiple states based on the first duration and the second duration.

6. The memory of claim 1 , wherein the first state comprises a set state and the second state comprises a reset state.

7. The memory of claim 1 , wherein the memory comprises an embedded memory.

8. A memory comprising:

a bit line;

a phase change element, a first side of the phase change element coupled to the bit line;

a first access device coupled to a second side of the phase change element;

a second access device coupled to the second side of the phase change element; and

a circuit for precharging the bit line and one of selecting the first access device to program the phase change element to a first state and selecting the second access device to program the phase change element to a second state.

9. The memory of claim 8 , wherein the first access device comprises a first transistor and the second access device comprises a second transistor.

10. The memory of claim 9 , further comprising:

a first word line coupled to a gate of the first transistor; and

a second word line coupled to a gate of the second transistor.

11. The memory of claim 10 , wherein the circuit selects the first transistor by applying a first pulse having a first duration to the first word line and selects the second transistor by applying a second pulse having a second duration to the second word line, wherein the circuit programs the phase change element to one of multiple states based on the first duration and the second duration.

12. The memory of claim 8 , wherein the first state comprises a set state and the second state comprises a reset state.

13. The memory of claim 8 , wherein the memory comprises an embedded memory.

14. A memory comprising:

a bit line;

a phase change element, a first side of the phase change element coupled to the bit line;

first means coupled to a second side of the phase change element for accessing the phase change element;

second means coupled to the second side of the phase change element for accessing the phase change element; and

means for precharging the bit line to a first voltage and one of selectively activating one of the first means and the second means individually and activating the first means and the second means simultaneously to program the phase change element to one of a first state and a second state.

15. The memory of claim 14 , wherein the first state comprises a crystalline state and the second state comprises an amorphous state.

16. The memory of claim 14 , wherein the memory comprises an embedded memory.