Shallow bipolar junction transistor

1. A shallow bipolar junction transistor comprising:

a high voltage n+ well implanted into a semiconductor substrate;

an oxide nitride oxide (ONO) layer, an n+ collector, and a bit line residual oxide removal (BLROE)/spacer over etch (SPXOE) layer above said high voltage n+ well;

a bit line n+ implant (BNI) above said high voltage n+ well, wherein a portion of said ONO layer is formed around a portion of said BNI;

a plurality of emitters in a central region of the transistor, a base laterally separated from the plurality of emitters, and an n+ core implant surrounding the plurality of emitters to isolate the base and the plurality of emitters, wherein the n+ core implant defines a difference between said base and an emitter;

a high voltage gate oxide (HVGOX) above said n+ collector and around said base; and

a p+ source/drain implant (PP) layer around said base.

2. The shallow bipolar junction transistor of claim 1 wherein said oxide nitride oxide (ONO) layer is at a periphery area of said BNI.

3. The shallow bipolar junction transistor of claim 1 further comprising a shallow trench isolation (STI) region proximate to said ONO layer.

4. The shallow bipolar junction transistor of claim 1 wherein said bit line n+ implant is at a periphery area of said plurality of emitters.

5. The shallow bipolar junction transistor of claim 4 further comprising an n+ implant for isolating a base and emitters of said shallow bipolar junction transistor.

6. The shallow bipolar junction transistor of claim 1 further comprising an emitter wherein a portion of said emitter is operable to operate as a contact.

7. The shallow bipolar junction transistor of claim 6 wherein said portion of said emitter is operable to operate as a contact without a cobalt silicide (CoSi) layer.