IP Library Granted Patent US 7,372,243
Granted Patent B2
US 7,372,243 · App. 11/657,021 · Granted May 13, 2008

Reference voltage circuit driven by non-linear current mirror circuit

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Quick Facts
Patent No.
US 7,372,243
App. No.
11/657,021
Granted
May 13, 2008
Kind
B2
Abstract

Disclosed is a reference voltage circuit which includes control means for exercising control so as to equalize a divided voltage that is output from a first current-to-voltage converting circuit having a diode-connected MOS transistor and voltage-dividing resistors and a divided voltage that is output from a second current-to-voltage converting circuit having a diode-connected MOS transistor and voltage-dividing resistors; a first current mirror circuit having a non-linear input/output characteristic for supplying currents to the first and second current-to-voltage converting circuits, respectively; a second current mirror circuit having a linear input/output characteristic for outputting a current proportional to the value of the current supplied to the first current-to-voltage converting circuit; and a third current mirror circuit having a linear input/output characteristic for outputting a current proportional to the value of the current supplied to the second current-to-voltage converting circuit. A third current-to-voltage converting circuit converts a current, which is the result of adding the output currents of the second and third current mirror circuits, to a voltage to supply the so converted voltage as a reference voltage.

Claims (40)

1. A reference voltage circuit comprising:

first and second current-to-voltage converting circuits, each of which receives a current and converts the current to a voltage;

a control circuit that exercises control in such a manner that a prescribed output voltage of said first current-to-voltage converting circuit and a prescribed output voltage of said second current-to-voltage converting circuit will become equal;

a first current mirror circuit that has a non-linear input/output characteristics and supplies currents to respective ones of said first and second current-to-voltage converting circuits;

a second current mirror circuit that has a linear input/output characteristic, and outputs a current which is proportional to a value of the current supplied to said first current-to-voltage converting circuit;

a third current mirror circuit that has a linear input/output characteristic, and outputs a current which is proportional to the value of the current supplied to said second current-to-voltage converting circuit; and

a third current-to-voltage converting circuit that receives a current which is the result of adding an output current from said second current mirror circuit and an output current from said third current mirror circuit and converts the current to a voltage which is supplied as a reference voltage.

2. The circuit according to claim 1 , wherein said third current-to-voltage converting circuit comprises a resistor.

3. The circuit according to claim 1 , wherein said first and second current-to-voltage converting circuits each include a diode-connected MOS transistor and a voltage-dividing resistor connected in parallel with said MOS transistor;

divided voltages from the voltage-dividing resistors of respective ones of said first and second current-to-voltage converting circuits being output as said output voltages of respective ones of said first and second current-to-voltage converting circuits.

4. The circuit according to claim 1 , wherein said first current-to-voltage converting circuit has a diode and a first voltage-dividing resistor connected in parallel with said diode; and

said second current-to-voltage converting circuit has a series circuit, which comprises one diode or a plurality of parallel-connected diodes and a resistor, and a second voltage-dividing resistor connected in parallel with said series circuit;

divided voltages from said first and second voltage-dividing resistors of respective ones of said first and second current-to-voltage converting circuits being output as said prescribed output voltages of respective ones of said first and second current-to-voltage converting circuits.

5. The circuit according to claim 4 , wherein said diode is composed by a diode-connected bipolar transistor.

6. The circuit according to claim 1 , wherein said control circuit includes a differential amplifying circuit having differential input terminals for receiving respective ones of the prescribed output voltages of said first and second current-to-voltage converting circuits, and an output terminal for delivering a voltage that controls a common node of said first to third current mirror circuits.

7. A reference voltage circuit comprising:

first to third current-to-voltage converting circuits;

first to fourth MOS transistors having gates coupled together; and

a differential amplifying circuit;

wherein sources of said first and third MOS transistors are connected to a first power supply via respective ones of resistors;

sources of said second and fourth MOS transistors are connected directly to the first power supply;

said first current-to-voltage converting circuit includes a fifth MOS transistor having a drain and a gate connected to a second power supply and a source connected to a drain of said first MOS transistor, and a first voltage-dividing resistor connected in parallel with said fifth MOS transistor;

said second current-to-voltage converting circuit includes a sixth MOS transistor having a drain and a gate connected to the second power supply and a source connected to a drain of said second MOS transistor, and a second voltage-dividing resistor connected in parallel with said sixth MOS transistor;

said third current-to-voltage converting circuit comprises a resistor having a first end connected to the second power supply;

divided voltages from the first and second voltage-dividing resistors of said first and second current-to-voltage converting circuits, respectively, are applied to respective ones of differential input terminals of said differential amplifying circuit, and an output terminal of said differential amplifying circuit is connected to the coupled gates of said first to fourth MOS transistors; and

drains of said third and fourth MOS transistors are coupled together and connected to a second end of said resistor of said third current-to-voltage converting circuit, and a voltage at a node of connection between drains of said third and fourth MOS transistors and said resistor of said third current-to-voltage converting circuit is output as a reference voltage.

8. The circuit according to claim 7 , wherein W/L ratios of said first, fifth and sixth MOS transistors are each a prescribed multiple of a W/L ratio of said second MOS transistor, which forms a unit transistor.

9. A reference voltage circuit comprising:

first to third current-to-voltage converting circuits;

first to fourth MOS transistors having gates coupled together; and

a differential amplifying circuit;

wherein sources of said first and third MOS transistors are connected to a first power supply via respective ones of resistors;

sources of said second and fourth MOS transistors are connected directly to the first power supply;

said first current-to-voltage converting circuit includes a diode having a cathode connected to a second power supply and an anode connected to a drain of said first MOS transistor, and a first voltage-dividing resistor connected in parallel with said diode;

said second current-to-voltage converting circuit includes: a series circuit, which comprises plurality of diodes having cathodes connected to the second power supply and anodes coupled together, and a resistor having a first end connected to a common node of the plurality of diodes and a second end connected to a drain of said second MOS transistor;

said third current-to-voltage converting circuit comprises a resistor having a first end connected to the second power supply;

divided voltages from said first and second voltage-dividing resistors of said first and second current-to-voltage converting circuits, respectively, are applied to respective ones of differential input terminals of said differential amplifying circuit, and an output terminal of said differential amplifying circuit is connected to the coupled gates of said first to fourth MOS transistors; and

drains of said third and fourth MOS transistors are coupled together and connected to a second end of said resistor of said third current-to-voltage converting circuit, and a voltage at a node of connection between drains of said third and fourth MOS transistors and said resistor of said third current-to-voltage converting circuit is output as a reference voltage.

10. The circuit according to claim 7 , wherein said first and second MOS transistors form a current mirror having a non-linear input/output characteristic, said first and third MOS transistors form a current mirror having a linear input/output characteristic, and said second and fourth MOS transistors form a current mirror having a linear input/output characteristic.

11. The circuit according to claim 9 , wherein said first and second MOS transistors form a current mirror having a non-linear input/output characteristic, said first and third MOS transistors form a current mirror having a linear input/output characteristic, and said second and fourth MOS transistors form a current mirror having a linear input/output characteristic.

Assignments (2)
CHANGE OF NAME Recorded Nov 4, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025311/0860 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2007
From: KIMURA, KATSUJI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 018834/0027 →