Semiconductor device and method of manufacturing the same
View Patent ↗The invention relates to a semiconductor device ( 10 ) with a substrate ( 11 ) and a semiconductor body ( 12 ) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region ( 1, 2, 3 ) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region ( 3 ) comprises a first sub-region ( 3 A) bordering the base region ( 2 ) and a second sub-region ( 3 B) bordering the first sub-region ( 3 A) which has a lower doping concentration than the second sub-region ( 3 B), and the transistor is provided with a gate electrode ( 5 ) which laterally borders the first sub-region ( 3 A) and by means of which the first sub-region ( 3 A) may be depleted. According to the invention the collector region ( 3 ) borders the surface of the semiconductor body ( 12 ), while the emitter region ( 1 ) is recessed in the semiconductor body ( 12 ), and the collector region ( 3 ) forms part of a mesa structure ( 6 ) formed at the surface of the semiconductor body ( 12 ). Such a device ( 10 ) has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector ( 3 ) comprises a nanowire ( 30 ) forming the mesa structure ( 6 ).
1. A semiconductor device with a substrate and a semiconductor body comprising a vertical bipolar transistor with an emitter region, a base region and a collector region of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region comprises a first sub-region bordering on the base region and a second sub-region bordering on the first sub-region which has a lower doping concentration than the second sub-region and the transistor is provided with a gate electrode which laterally borders on the first sub-region and by means of which the first sub-region can be depleted, characterized in that the collector region borders on the surface of the semiconductor body while the emitter region is recessed in the semiconductor body and the collector region forms part of a mesa structure formed at the surface of the semiconductor body, wherein the gate electrode is separated from the semiconductor body by an insulating layer.
2. A semiconductor device as claimed in claim 1 , characterized in that the base region and the collector region are formed in a semiconductor layer structure which is provided on the emitter region and in which the mesa structure is formed by means of etching.
3. A semiconductor device as claimed in claim 1 , characterized in that the base region is formed by means of a layer-shaped region at the surface of the semiconductor body, the emitter region is formed in the semiconductor body under the base region and the mesa structure comprises a nanowire which is provided on the surface of the semiconductor body in such a manner that its longitudinal axis extends perpendicularly to the surface thereof.
4. A semiconductor device as claimed in claim 3 , characterized in that the nanowire is formed by means of a selective deposition process.
5. A semiconductor device as claimed in claim 3 , characterized in that the nanowire comprises a semiconductor material with a larger bandgap than the semiconductor material of the semiconductor body.
6. A semiconductor device as claimed in claim 3 , characterized in that the nanowire is provided with a spacer and the base region is formed in a self-aligning manner with respect to the nanowire provided with the spacer.
7. A semiconductor device as claimed in claim 1 , characterized in that the base region and the gate electrode have a common connection.
8. A semiconductor device as claimed in claim 1 , characterized in that the semiconductor body contains silicon.
9. A semiconductor device as claimed in claim 1 , characterized in that the base region contains a mixed crystal of SiGe.
10. A semiconductor device as claimed in claim 9 , characterized in that the base region has a thickness of approximately 20 nanometers.
11. A semiconductor device as claimed in claim 1 , characterized in that the base region contains a mixed crystal of Si and C.
12. A semiconductor device as claimed in claim 1 , characterized in that the base region contains pure Si.
13. A semiconductor device as claimed in claim 1 , characterized in that the gate electrode is in the form of a semi-insulating polycrystalline silicon.
14. A semiconductor device as claimed in claim 1 , characterized in that the gate electrode is based on a p-i-n diode.
15. A semiconductor device as claimed in claim 1 , characterized in that the mesa structure comprises a nanowire that is buried by an electrically conductive layer and another insulating layer.
16. A semiconductor device with a substrate and a semiconductor body comprising a vertical bipolar transistor with an emitter region, a base region and a collector region of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region comprises a first sub-region bordering on the base region and a second sub-region bordering on the first sub-region which has a lower doping concentration than the second sub-region and the transistor is provided with a gate electrode which laterally borders on the first sub-region and by means of which the first sub-region can be depleted, characterized in that the collector region borders on the surface of the semiconductor body while the emitter region is recessed in the semiconductor body and the collector region forms part of a mesa structure formed at the surface of the semiconductor body, characterized in that the base region is formed by means of a layer-shaped region at the surface of the semiconductor body, the emitter region is formed in the semiconductor body under the base region and the mesa structure comprises a nanowire which is provided on the surface of the semiconductor body in such a manner that its longitudinal axis extends perpendicularly to the surface thereof, wherein the nanowire is buried by an electrically conductive layer and an insulating layer.
17. A semiconductor device as claimed in claim 16 , characterized in that the nanowire is formed by means of a selective deposition process.
18. A semiconductor device as claimed in claim 17 , characterized in that the nanowire comprises a semiconductor material with a larger bandgap than the semiconductor material of the semiconductor body.
19. A semiconductor device as claimed in claim 18 , characterized in that the nanowire is provided with a spacer and the base region is formed in a self-aligning manner with respect to the nanowire provided with the spacer.
20. A semiconductor device as claimed in claim 16 , characterized in that the base region and the collector region are formed in a semiconductor layer structure which is provided on the emitter region and in which the mesa structure is formed by means of etching.