Stacked packaging improvements
A plurality of microelectronic assemblies ( 60 ) are made by severing an in-process unit including an upper substrate ( 40 ) and lower substrate ( 20 ) with microelectronic elements ( 36 ) disposed between the substrates. In a further embodiment, a lead frame ( 452 ) is joined to a substrate ( 440 ) so that the leads project from this substrate. Lead frame ( 452 ) is joined to a further substrate ( 470 ) with one or more microelectronic elements ( 436, 404, 406 ) disposed between the substrates.
1. An in-process unit including upper and lower dielectric substrates and a plurality of microelectronic elements disposed between said upper and lower dielectric substrates, each said microelectronic element comprising a semiconductor chip, each of said upper and lower dielectric substrates including a plurality of regions, each region of said upper dielectric substrate being aligned with a corresponding region of the lower dielectric substrate with at least one said microelectronic element disposed therebetween, each of said regions of said upper and lower dielectric substrates having electrically conductive elements thereon, said in-process unit further including wire bonds having first ends joined to at least some of said conductive elements of each said region of said upper dielectric substrate and second ends joined to the electrically conductive elements of the corresponding region of said lower dielectric substrate, said wire bonds electrically connecting said regions of said upper substrate with said corresponding regions of said lower substrates such that each said wire bond has a first end joined to one said conductive element of one said region of said upper dielectric substrate and has a second end joined to one said conductive element of one said region of said lower dielectric substrate.
2. An in-process unit as claimed in claim 1 further comprising an encapsulant disposed at least between said upper and lower dielectric substrates.
3. An in-process unit, comprising:
a lower dielectric substrate having a plurality of regions;
a plurality of upper dielectric substrates, each aligned with a respective region of said lower dielectric substrate; and
a plurality of microelectronic elements each comprising a semiconductor chip, each microelectronic element disposed between one of said upper dielectric substrates and said respective region of said lower dielectric substrate,
each of said upper dielectric substrates and said regions of said lower dielectric substrate having electrically conductive elements thereon, said in-process unit further comprising wire bonds having first ends joined to at least some of said conductive elements of each said upper substrate and second ends joined to said electrically conductive elements of said respective region of said lower substrate, said wire bonds electrically connecting said conductive elements of said upper dielectric substrates with said respective regions of said lower dielectric substrate such that each said wire bond has a first end joined to one said conductive element of one of said upper dielectric substrates and has a second end joined to one said conductive element of one said region of said lower dielectric substrate.
4. An in-process unit as claimed in claim 3 further comprising an encapsulant disposed at least between each said upper dielectric substrate and said respective region of said lower dielectric substrate.
5. An in-process unit, comprising:
an upper dielectric substrate having a plurality of regions;
a plurality of lower dielectric substrates, each aligned with a respective region of said upper dielectric substrate; and
a plurality of microelectronic elements, each disposed between one of said lower dielectric substrates and said respective region of said upper dielectric substrate, each said microelectronic element comprising a semiconductor chip,
each of said lower dielectric substrates and said regions of said upper dielectric substrate having electrically conductive elements, said in-process unit having a plurality of wire bonds electrically connecting at least some of said conductive elements of each said lower dielectric substrate with said electrically conductive elements of said respective region of said upper dielectric substrate such that each said wire bond has a first end joined to one said conductive element of said upper dielectric substrate and has a second end joined to one said conductive element of one of said lower dielectric substrates.
6. An in-process unit as claimed in claim 5 further comprising an encapsulant disposed at least between each said lower dielectric substrate and said respective region of said upper dielectric substrate.