DIAGNOSTIC/PROTECTIVE HIGH VOLTAGE GATE DRIVER IC (HVIC) FOR PDP

1 . A PDP sustain driver circuit including at least one high voltage gate driver IC (HVIC) having internal logic functions, the circuit comprising:

a plurality of electronic switches, the HVIC providing a unique control signal to at least one first and at least one second switch;

the internal logic functions comprising:

a sensing circuit for sensing information about the at least one second switch; and

a reporting circuit for reporting or displaying a signal indicating at least one of a plurality of failure modes of the at least one second switch.

2 . The circuit of claim 1 , the internal logic functions further comprising

an estimating circuit for receiving the sensed information and estimating a failure condition;

a diagnosing circuit for receiving the sensed information and the estimated failure condition and diagnosing the at least one failure mode; and

a protection circuit for commanding the gate driver to shut-down or self restart in accordance with the failure mode,

wherein the diagnosing circuit alerts the reporting and protection circuits to report or display the failure mode and to issue the shut-down or self restart commands.

3 . The circuit of claim 1 , wherein the plurality of switches includes rising, falling, sustain, and ground switches, each switch being driven by a unique signal connected to the switch's gate.

4 . The circuit of claim 3 , wherein the rising and falling switches are coupled in a half-bridge and the sustain and ground switches are coupled in a second half-bridge.

5 . The circuit of claim 4 , wherein the second half-bridge is integrated in the HVIC.

6 . The circuit of claim 2 , wherein the estimated failure condition is selected from an estimation of a power loss and a thermal condition of the switch.

7 . The circuit of claim 1 , wherein the sensing information is selected from a current value, a voltage value, variation of the current value, variance of the voltage value, temperature, and ambient temperature of at least one second switch.

8 . The circuit of claim 1 , wherein the system information and the at least one failure mode are reported to a system controller.

9 . The circuit of claim 1 , further comprising a signal buffer for receiving at most two input signals and providing the at most two signals to a gate driver.

10 . The circuit of claim 1 , wherein the PDP sustain driver is a bridge driver with soft switching for a capacitive load.

11 . The circuit of claim 2 , wherein the HVIC integrates any two or more circuits selected from the sensing, estimating, diagnostic, reporting, and protecting circuits.

12 . The circuit of claim 11 , comprising at least two HVICs.