MOS transistor and manufacturing methods thereof

1. A method for manufacturing a MOS transistor comprising steps of:

providing a substrate having at least a gate structure having a hard mask layer and a cap layer formed thereon and a shallow trench isolation (STI);

performing a first etching process to form recesses in the substrate respectively on two sides of the gate structure;

performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, a seam being accordingly formed between the epitaxial silicon layer and the STI;

performing a deposition process to deposit a dielectric layer on the substrate, the dielectric layer filling the seams;

performing a second etching process to remove the dielectric layer except the seams, the hard mask layer, and the cap layer after the deposition process; and

performing a self-aligned silicidation (salicide) process.

2. The method of claim 1 wherein the gate structure further comprises:

a gate dielectric layer;

a gate conductive layer formed on the gate dielectric layer; and

a spacer formed on sidewalls of the gate conductive layer.

3. The method of claim 1 further comprising a first pre-cleaning step performed after the first etching process to remove residuals from the substrate and the recesses.

4. The method of claim 1 further comprising a step of forming a salicide barrier (SAB) layer before performing the salicide process.

5. The method of claim 4 further comprising a second pre-cleaning step performed after forming the SAB layer to remove residuals from the substrate, the gate structure, and the epitaxial silicon layers.

6. The method of claim 4 wherein the SAB layer comprises silicon dioxide or silicon nitride.

7. The method of claim 1 wherein the dielectric layer comprises silicon oxide, silicon oxynitride, or silicon nitride.

8. The method of claim 1 wherein the deposition process further comprises a high density plasma chemical vapor deposition (HDP-CVD), atmosphere pressure chemical vapor deposition (APCVD), sub-atmosphere chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

9. The method of claim 1 wherein the second etching process comprises a dry etching process or a wet etching process.

10. The method of claim 1 wherein the gate structure is a gate structure of a PMOS transistor.

11. The method of claim 10 , wherein the epitaxial silicon layer comprises silicon germanium (SiGe).

12. The method of claim 10 , wherein the epitaxial silicon layer comprises silicon carbide (SiC).

13. The method of claim 1 wherein the gate structure is a gate structure of an NMOS transistor.