IP Library Granted Patent US 7,544,997
Granted Patent B2
US 7,544,997 · App. 11/676,114 · Granted Jun 9, 2009

Multi-layer source/drain stressor

Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 7,544,997
App. No.
11/676,114
Granted
Jun 9, 2009
Kind
B2
Abstract

A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.

Claims (31)

1. A method for forming a semiconductor device comprising:

forming a recess in a source region and a recess in a drain region of the semiconductor device;

forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material;

forming a third semiconductor material layer overlying the first semiconductor material layer and a fourth semiconductor material layer overlying the second semiconductor material layer, wherein each of the third semiconductor material layer and the fourth semiconductor material layer have a second ratio of the atomic concentration of the first element and the atomic concentration of the second element, wherein the second ratio is higher than the first ratio and wherein each of the third semiconductor material layer and the fourth semiconductor material layer have a second level of concentration of the doping material, wherein the second level of concentration of the doping material is higher than the first level of concentration of the doping material; and

forming a fifth semiconductor material layer overlying the third semiconductor material layer and a sixth semiconductor material layer overlying the fourth semiconductor material layer, wherein each of the fifth semiconductor material layer and the sixth semiconductor material layer have a third ratio of the atomic concentration of the first element and the atomic concentration of the second element, wherein the third ratio is lower than the second ratio and wherein each of the fifth semiconductor material layer and the sixth semiconductor material layer have a third level of concentration of the doping material, wherein the third level of concentration of the doping material is higher than the second level of concentration of the doping material.

2. The method of claim 1 , wherein the stressor material is an alloy of silicon and germanium such that the second element is germanium.

3. The method of claim 1 , wherein the doping material is one or more of a group V element.

4. The method of claim 3 , wherein the first ratio of the atomic concentration of the first element to the atomic concentration of the second element is about 2.3 to 1.

5. The method of claim 3 , wherein the doping material is boron and the first level of concentration of the doping material is from about 5e19 atoms per cm 3 to about 2e20 atoms per cubic centimeter.

6. The method of claim 3 , wherein the second ratio of the atomic concentration of the first element to the atomic concentration of the second element is about 3.0 to 1.

7. The method of claim 3 , wherein the doping material is boron and the second level of concentration of the doping material is from about 2e20 atoms per cm 3 to 5e20 atoms per cubic centimeter.

8. The method of claim 3 , wherein the third ratio of the atomic concentration of the first element to the atomic concentration of the second element is about 2.3 to 1.

9. The method of claim 3 , wherein the doping material is boron and the third level of concentration of the doping material is in a range from about 5e20 atoms per cm 3 to 1e21 atoms per cm 3 .

10. A method for forming a semiconductor device comprising:

forming a recess in a source region and a recess in a drain region of the semiconductor device;

forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and wherein each of the first semiconductor material layer and the second semiconductor material layer have a first level of concentration of a doping material;

forming a third semiconductor material layer overlying the first semiconductor material layer and a fourth semiconductor material layer overlying the second semiconductor material layer, wherein each of the third semiconductor material layer and the fourth semiconductor material layer have a second level of concentration of the doping material, wherein the second level of concentration of the doping material is higher than the first level of concentration of the doping material; and

forming a fifth semiconductor material layer overlying the third semiconductor material layer and a sixth semiconductor material layer overlying the fourth semiconductor material layer, wherein each of the fifth semiconductor material layer and the sixth semiconductor material layer have a third level of concentration of the doping material, wherein the third level of concentration of the doping material is higher than the second level of concentration of the doping material.

11. The method of claim 10 , wherein the doping material is one or more of a group V element.

12. The method of claim 11 , wherein the doping material is boron and the first level of concentration of the doping material is from about 5e19 atoms per cm 3 to about 2e20 atoms per cm 3 .

13. The method of claim 11 , wherein the second level of concentration of the doping material is from about 2e20 atoms per cm 3 to 5e20 atoms per cm 3 .

14. The method of claim 11 , wherein the third level of concentration of the doping material is in a range from about 5e20 atoms per cm 3 to 1e21 atoms per cm 3 .

15. A semiconductor device comprising:

a first semiconductor material layer in a recess in a source region and a second semiconductor material layer in a recess in a drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element and a first level of concentration of a doping material, wherein the first element is silicon;

a third semiconductor material layer overlying the first semiconductor material layer and a fourth semiconductor material layer overlying the second semiconductor material layer, wherein each of the third semiconductor material layer and the fourth semiconductor material layer have a second ratio of the atomic concentration of the first element and the atomic concentration of the second element, wherein the second ratio is higher than the first ratio and wherein each of the third semiconductor material layer and the fourth semiconductor material layer have a second level of concentration of the doping material, wherein the second level of concentration of the doping material is higher than the first level of concentration of the doping material; and

a fifth semiconductor material layer overlying the third semiconductor material layer and a sixth semiconductor material layer overlying the fourth semiconductor material layer, wherein each of the fifth semiconductor material layer and the sixth semiconductor material layer have a third ratio of the atomic concentration of the first element and the atomic concentration of the second element, wherein the third ratio is lower than the second ratio and wherein each of the fifth semiconductor material layer and the sixth semiconductor material layer have a third level of concentration of the doping material, wherein the third level of concentration of the doping material is higher than the second level of concentration of the doping material.

16. The semiconductor device of claim 15 , wherein the stressor material is an alloy of silicon and germanium such that the second element is germanium.

17. The semiconductor device of claim 15 , wherein the doping material is one or more of a group V.

18. The semiconductor device of claim 17 , wherein the first ratio of the atomic concentration of the first element to the atomic concentration of the second element is about 2.3 to 1.

19. The semiconductor device of claim 17 , wherein the doping material is boron and the first level of concentration of the doping material is from about 5e19 atoms per cm 3 to about 2e20 atoms per cm 3 , the second level of concentration of the doping material is from about 2e20 atoms per cm 3 to 5e20 atoms per cm 3 , and the third level of concentration of the doping material is in a range from about 5e20 atoms per cm 3 to 1e21 atoms per cm 3 .

20. The semiconductor device of claim 17 , wherein the second ratio of the atomic concentration of the first element to the atomic concentration of the second element is about 3.0 to 1.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0640 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Sep 23, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023273/0099 →
SECURITY AGREEMENT Recorded Sep 19, 2007
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 019847/0804 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2007
From: ZHANG, DA; DHANDAPANI, VEERARAGHAVAN; GOEDEKE, DARREN V.; HILDRETH, JILL C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018900/0319 →
Continuity (1)
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