Method of wire bonding over active area of a semiconductor circuit
View Patent ↗A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
1. A circuit component comprising:
a semiconductor substrate;
a first active device in or over said semiconductor substrate;
a first dielectric layer over said semiconductor substrate and over said first active device;
a first interconnect metal layer over said first dielectric layer and over said semiconductor substrate;
a second dielectric layer over said first interconnect metal layer and over said first dielectric layer;
a second interconnect metal layer over said second dielectric layer;
a passivation layer on said second interconnect metal layer and over said second dielectric layer, wherein a first opening in said passivation layer is over a contact point of said second interconnect metal layer, and wherein said passivation layer comprises a nitride;
a polymer layer on said passivation layer, wherein said polymer layer has a thickness greater than 2 micrometers and greater than that of said passivation layer;
a metal pad on said polymer layer and over said first active device, wherein said metal pad is connected to said contact point through said first opening, and wherein said metal pad comprises a glue/barrier layer, a gold seed layer over said glue/barrier layer, and an electroplated gold layer having a thickness greater than 1 micrometer over said gold seed layer; and
a wire bonded to said metal pad, wherein a contact between said wire and said metal pad is directly over said first active device and over said polymer layer, wherein said contact has a transverse dimension greater than that of said first opening.
2. The circuit component of claim 1 , wherein said electroplated gold layer has a hardness less than 150 Hv.
3. The circuit component of claim 1 , wherein said glue/barrier layer comprises a titanium-containing layer under said gold seed layer.
4. The circuit component of claim 1 , wherein said glue/barrier layer comprises a titanium-tungsten-alloy layer under said gold seed layer.
5. The circuit component of claim 1 , wherein said electroplated gold layer comprises a gold purity greater than 97%.
6. The circuit component of claim 1 , wherein said glue/barrier layer comprises a titanium-nitride layer under said gold seed layer.
7. The circuit component of claim 1 , wherein said contact is further directly over a portion of said second interconnect metal layer.
8. The circuit component of claim 1 further comprising a second active device in or over said semiconductor substrate and under said first dielectric layer, wherein said second active device comprises a portion directly under said contact point.
9. The circuit component of claim 1 , wherein said polymer layer comprises polyimide.
10. The circuit component of claim 1 , wherein said polymer layer comprises benzocyclobutcne (BCB).
11. The circuit component of claim 1 , wherein said nitride comprises silicon nitride.
12. The circuit component of claim 1 , wherein a second opening in said polymer layer is over said contact point, wherein said metal pad is connected to said contact point further through said second opening.
13. The circuit component of claim 1 , wherein said passivation layer further comprises an oxide under said nitride.