Method for fabricating strained-silicon metal-oxide semiconductor transistors
View Patent ↗A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.
1. A method for fabricating a strained-silicon metal-oxide semiconductor transistor, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate;
forming a lightly doped drain in the semiconductor substrate after forming the gate structure;
forming a spacer around the gate structure;
forming a source/drain region in the semiconductor substrate surrounding the spacer;
performing a first rapid thermal annealing process for activating the dopants within the source/drain region and the lightly doped drain;
performing an etching process for forming a recess on the gate structure and the source/drain region surrounding the gate structure respectively;
performing a selective epitaxial growth process for forming an epitaxial layer in each recess; and
performing a second rapid thermal annealing process on the source/drain region and the lightly doped drain for redefining the distribution of dopants within the source/drain region and the lightly doped drain and repairing the damaged bonds within the dopants.
2. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 , wherein the gate structure comprises:
a gate dielectric; and
a gate disposed on the gate dielectric.
3. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 further comprising forming a lightly doped drain in the semiconductor substrate after forming the gate structure on the semiconductor substrate.
4. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 , wherein the temperature of the first rapid thermal annealing process and the second rapid thermal annealing process is between 900 degrees to 1100 degrees.
5. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 , wherein the duration of the first rapid thermal annealing process and the second rapid thermal annealing process is between 10 seconds to 30 seconds.
6. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 further comprising performing a millisecond annealing process after the second rapid thermal annealing process.
7. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 6 , wherein the temperature of the millisecond annealing process is between 1000 degrees to 1350 degrees.
8. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 6 , wherein the duration of the millisecond annealing process is between 100 milliseconds to 1 microsecond.
9. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 further comprising performing a baking process before forming the epitaxial layer.
10. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 9 , wherein the temperature of the baking process is between 700 degrees to 950 degrees.
11. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 , wherein the strained-silicon metal-oxide semiconductor transistor is a PMOS transistor.
12. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 11 , wherein the epitaxial layer comprises silicon germanium.
13. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 1 , wherein the strained-silicon metal-oxide semiconductor transistor is an NMOS transistor.
14. The method for fabricating a strained-silicon metal-oxide semiconductor transistor of claim 13 , wherein the epitaxial layer comprises silicon carbide.
15. A method for fabricating a strained-silicon CMOS transistor, comprising:
providing a semiconductor substrate having a first active region for fabricating a first transistor, a second active region for fabricating a second transistor, and an insulating structure disposed between the first active region and the second active region;
forming a first gate structure on the first active region and a second gate structure on the second active region;
forming a lightly doped drain for the first transistor and a lightly doped drain for the second transistor;
forming a spacer around the first gate structure and the second gate structure respectively;
forming a source/drain region for the first transistor and a source/drain region for the second transistor;
performing a first rapid thermal annealing process for activating the dopants within the source/drain region and the lightly doped drain;
performing an etching process for forming a first recess on the first gate structure and in the source/drain region surrounding the first gate structure and a second recess on the second gate structure and in the source/drain region surrounding the second gate structure;
performing a baking process and then a selective epitaxial growth process for forming a first epitaxial layer in the first recess and a second epitaxial layer in the second recess; and
performing a second rapid thermal annealing process on the source/drain region and the lightly doped drain after the baking process for redefining the distribution of dopants within the source/drain regions and the lightly doped drain and repairing the damaged bonds within the dopants.
16. The method for fabricating a strained-silicon CMOS transistor of claim 15 , wherein the first gate structure comprises:
a first gate dielectric; and
a first gate disposed on the first gate dielectric.
17. The method for fabricating a strained-silicon CMOS transistor of claim 15 , wherein the second gate structure comprises:
a second gate dielectric; and
a second gate disposed on the second dielectric.
18. The method for fabricating a strained-silicon CMOS transistor of claim 15 , wherein the temperature of the first rapid thermal annealing process and the second rapid thermal annealing process is between 900 degrees to 1100 degrees.
19. The method for fabricating a strained-silicon CMOS transistor of claim 15 , wherein the duration of the first rapid thermal annealing process and the second rapid thermal annealing process is between 10 seconds to 30 seconds.
20. The method for fabricating a strained-silicon CMOS transistor of claim 15 further comprising performing a millisecond annealing process after the second rapid thermal annealing process.
21. The method for fabricating a strained-silicon CMOS transistor of claim 20 , wherein the temperature of the millisecond annealing process is between 1000 degrees to 1350 degrees.
22. The method for fabricating a strained-silicon CMOS transistor of claim 20 , wherein the duration of the millisecond annealing process is between 100 milliseconds to 1 microsecond.
23. The method for fabricating a strained-silicon CMOS transistor of claim 15 , wherein the temperature of the baking process is between 700 degrees to 950 degrees.
24. The method for fabricating a strained-silicon CMOS transistor of claim 15 , wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.
25. The method for fabricating a strained-silicon CMOS transistor of claim 24 , wherein the first epitaxial layer comprises silicon carbide.
26. The method for fabricating a strained-silicon CMOS transistor of claim 24 , wherein the second epitaxial layer comprises silicon germanium.
27. A method for fabricating a strained-silicon metal-oxide semiconductor transistor, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate;
forming a lightly doped drain in the semiconductor substrate after forming the gate structure;
forming a spacer around the gate structure;
forming a source/drain region in the semiconductor substrate surrounding the spacer, wherein the source/drain region excludes the lightly doped drain;
performing a first rapid thermal annealing process for activating the dopants within the source/drain region and the lightly doped drain;
performing an etching process for forming a recess on the gate structure and the source/drain region surrounding the gate structure respectively;
performing a selective epitaxial growth process for forming an epitaxial layer in each recess; and
performing a second rapid thermal annealing process on the source/drain region and the lightly doped drain for redefining the distribution of dopants within the source/drain region and the lightly doped drain and repairing the damaged bonds within the dopants.