Low dropout voltage regulator for slot-based operation

1. Voltage regulator for providing an output voltage (Vout) to a load (Zload), comprising an output transistor (T 1 ), an operational amplifier (OA), a floating voltage source (FVS; C 1 ) and a first reference voltage source (VS);

the output transistor (T 1 ) being connected via a drain terminal (D) to a voltage supply (Vsup), and via a source terminal (S) being connectable to a supply terminal (X 1 ) of the load (Zload);

a first input (IN 1 ) of the operational amplifier (OA) being connected to a feedback line (FL) to receive an input voltage derived from said source terminal (S);

the first reference voltage source (VS) being arranged for providing a reference voltage (Vref) to a second input (IN 2 ) of the operational amplifier (OA);

an output (O 1 ) of the operational amplifier (OA) being connected to a first terminal (F 1 ) of the floating voltage source (FVS; C 1 ), the output of the operational amplifier being arranged for providing an output voltage to the first terminal, and the floating voltage source having a second terminal (F 2 ) connected to a gate terminal (G) of the output transistor (T 1 );

the floating voltage source (FVS) being arranged for providing a voltage level (Vg) at the gate terminal of the output transistor (T 1 ) higher than said output voltage of said operational amplifier (OA).

2. Voltage regulator according to claim 1 , wherein the floating voltage source (FVS) is a storage capacitor (C 1 ), the first terminal (F 1 ) of the storage capacitor (C 1 ) also being connected to a first terminal of a first switching element (SW 1 ) and a second terminal of the first switching element (SW 1 ) being connected to ground potential (Vgnd);

the second terminal (F 2 ) of the storage capacitor (C 1 ) further being connected to a first terminal of a second switching element (SW 2 ), a second terminal of the second switching element (SW 2 ) being connected to a positive terminal of a second reference voltage source (VS 2 ) and a second terminal of the second reference voltage source (VS 2 ) being connected to ground potential;

the first and second switching elements (SW 1 , SW 2 ) being closed during a power-down mode of the voltage regulator.

3. Voltage regulator according to claim 2 , wherein the feedback line (FL) comprises a first resistor (R 1 ) of a resistive voltage divider (R 1 , R 2 ), a first terminal of the first resistor (R 1 ) being connected to the source terminal (S) of the output transistor (T 1 ), a second terminal of the first resistor (R 1 ) being connected to the first input (IN 1 ) of the operational amplifier (OA) and being connected to a first terminal of a second resistor (R 2 ), a second terminal of the second resistor (R 2 ) being connected to ground potential (Vgnd).

4. Voltage regulator according to claim 2 , wherein a third switching element (SW 3 ) is provided in the connection between the second input (IN 2 ) of the operational amplifier (OA) and the reference voltage source (VS), and

wherein the second input (IN 2 ) of the operational amplifier (OA) is further connected to a first terminal of a further capacitor (C 3 ), the further capacitor having a second terminal connected to ground potential (Vgnd).

5. Voltage regulator according to claim 4 , wherein a switching operation of at least one of the first, second, and third switching element (SW 1 ; SW 2 ; SW 3 ) is controlled by a first, second and third logical signal (L 1 ; L 2 ; L 3 ) respectively.

6. Voltage regulator according to claim 3 , wherein the first terminal (F 1 ) of the storage capacitor (C 1 ) is further connected to a first terminal of a still further capacitor (C 2 ) and a second terminal of the still further capacitor is connected to ground potential (Vgnd).

7. Voltage regulator according to claim 2 , wherein the second switching element (SW 2 ) is a diode, and the second reference voltage (Vref 2 ) as provided by the second reference voltage source (VS 2 ) is increased by an amount equal to a forward voltage of the diode.

8. Voltage regulator according to claim 1 , wherein a third input (IN 3 ) of the operational amplifier (OA) is connected to receive a supply voltage derived from the source terminal (S) of the output transistor (T 1 ) for the operational amplifier.

9. A voltage regulator (LD 1 ) according to claim 1 , wherein a further voltage regulator (LD 2 ) with a further drop-out voltage is connected in a cascade, the output of the source terminal (S) of the output transistor (T 1 ) of the voltage regulator (LD 1 ) providing a further voltage supply to the further voltage regulator (LD 2 ); the output voltage at the source terminal (S) of the output transistor (T 1 ) of the voltage regulator (LD 1 ) being, in use, higher than the further drop-out voltage of the second voltage regulator (LD 2 ).

10. Voltage regulator according to claim 1 , integrated in a system-on-chip.

11. Semiconductor device comprising at least one voltage regulator according to claim 1 .

12. Method of time-slot based operation for a voltage regulator for providing an output voltage (Vout) to a load (Zload), the voltage regulator comprising an output transistor (T 1 ), an operational amplifier (OA), a floating voltage source (FVS; C 1 ) and a first reference voltage source (VS);

the output transistor (T 1 ) being connected via a drain terminal (D) to a voltage supply (Vsup), and via a source terminal (S) being connectable to a supply terminal (X 1 ) of the load (Zload);

a first input (IN 1 ) of the operational amplifier (OA) being connected to a feedback line (FL) to receive an input voltage derived from said source terminal (S);

the first reference voltage source (VS) being arranged for providing a reference voltage (Vref) to a second input (IN 2 ) of the operational amplifier (OA);

an output (O 1 ) of the operational amplifier (OA) being connected to a first terminal (F 1 ) of the floating voltage source (FVS; C 1 ), the output of the operational amplifier being arranged for providing an output voltage to the first terminal, and the floating voltage source having a second terminal (F 2 ) being connected to a gate terminal (G) of the output transistor (T 1 );

the floating voltage source (FVS) being arranged for providing a voltage level (Vg) at the gate terminal of the output transistor (T 1 ) higher than said output voltage of said operational amplifier (OA), and

the floating voltage source (FVS) being a storage capacitor (C 1 ), the first terminal (F 1 ) of the storage capacitor (C 1 ) also being connected to a first terminal of a first switching element (SW 1 ) and a second terminal of the first switching element (SW 1 ) being connected to ground potential (Vgnd);

the second terminal (F 2 ) of the storage capacitor (C 1 ) further being connected to a first terminal of a second switching element (SW 2 ), a second terminal of the second switching element (SW 2 ) being connected to a positive terminal of a second reference voltage source (VS 2 ) and a second terminal of the second reference voltage source (VS 2 ) being connected to ground potential;

the first and second switching elements (SW 1 , SW 2 ) being closed during a power-down mode of the voltage regulator,

wherein

at a power-down period, said first and second switching elements (SW 1 , SW 2 ) are closed;

at a pre-charge step at a first time (t 0 ), the second switching element (SW 2 ) is opened;

at a power-on step at a second time (t 1 ), the first switching element (SW 1 ) is opened, with t 1 >t 0 .

13. Method of time-slot based operation for a voltage regulator according to claim 12 , wherein

the voltage regulator comprises a third switching element (SW 3 ) in the connection between the second input (IN 2 ) of the operational amplifier (OA) and the reference voltage source (VS), and

at a sampling step at a third time (t 3 ), the third switching element (SW 3 ) is opened, with t 3 >t 1 .

14. Method of time-slot based operation for a voltage regulator according to claim 12 , wherein at a fourth time (t 4 ), at least the first and third switching elements (SW 1 ; SW 3 ) are closed, with t 4 >t 3 .

15. Method of time-slot based operation for a voltage regulator according to claim 12 , wherein at a fifth time (t 5 ) the second switching element (SW 2 ) is closed, the fifth time being either simultaneous with or later than the fourth time (t 4 ).

16. Method of time-slot based operation for a voltage regulator according to claim 12 , wherein opening or closing of at least one of the first, second, and third switching element (SW 1 ; SW 2 ; SW 3 ) is controlled by a first, second and third logical signal (L 1 ; L 2 ; L 3 ) respectively.