Method of manufacturing a SONOS memory
View Patent ↗A method of manufacturing a silicon-oxide-nitride-oxide-silicon (SONOS) memory is provided herein. In the method, a bottom silicon oxide layer is formed over a substrate. A patterned mask layer having a trench therein is formed over the bottom silicon oxide layer. A charge-trapping layer is formed over the substrate covering the surface of the trench. The charge-trapping layer is etched back to form a pair of charge storage spacers on the sidewalls of the trench. After removing the mask layer, a top silicon oxide layer is formed over the substrate covering the charge storage spacers and the bottom silicon oxide layer. A gate corresponding to the pair of charge storage spacers is formed on the top silicon oxide layer. A source/drain region is formed in the substrate on each side of the gate.
1. A method of fabricating a silicon-oxide-nitride-oxide-silicon (SONGS) memory, comprising:
providing a substrate;
forming a bottom silicon oxide layer over the substrate;
forming a patterned mask layer over the bottom silicon oxide layer, wherein the patterned mask layer has a trench;
forming a charge-trapping layer over the substrate to cover the surface of the trench;
removing a portion of the charge-trapping layer to form a pair of charge storage spacers on the sidewalls of the trench;
removing the patterned mask layer;
forming a top silicon oxide layer over the substrate to cover the pair of charge storage spacers and the bottom silicon oxide layer;
forming a gate over the top silicon oxide layer above the pair of charge storage spacers;
forming a pair of dielectric spacers on the sidewalls of the gate;
removing portions of the top silicon oxide layer and the underlying bottom silicon oxide layer by using the dielectric spacers and the gate as hard masks, so as a surface of the substrate is exposed; and
forming source/drain regions in the substrate on each side of the gate.
2. The method of claim 1 , wherein the patterned mask layer is a silicon oxynitride layer or a silicon nitride layer.
3. The method of claim 1 , wherein the charge-trapping layer is a silicon nitride layer or a silicon oxynitride layer.