High linearity, low noise figure, front end circuit with fine step gain control

1. An electrical circuit comprising:

a low noise amplifier (LNA) signal line path comprising:

an LNA; and

a first signal mixer operatively connected to said LNA;

an attenuator signal line path comprising:

an attenuator; and

a second signal mixer operatively connected to said attenuator;

a radio frequency (RF) power detector operatively connected to an output of each of said LNA and said attenuator, wherein said RF power detector varies a front end power gain of said electrical circuit; and

logic circuitry operatively connected to said RF power detector, wherein said logic circuitry (i) selects transmission of a signal through only one of said LNA signal line path or said attenuator signal line path, and (ii) outputs the selected signal.

2. The electrical circuit of claim 1 , wherein said logic circuitry receives instructions from said RF power detector to switch between a LNA signal domain and an attenuator signal domain.

3. The electrical circuit of claim 1 , wherein a power gain of said LNA is stepped such that signal glitches through the outputted selected signal is minimized.

4. The electrical circuit of claim 1 , wherein said attenuator comprises a matching resistor in shunt with a signal through said attenuator signal line path.

5. The electrical circuit of claim 1 , wherein said attenuator comprises a resistive divider configuration comprising transistor switches in shunt with a signal through said attenuator signal line path.

6. The electrical circuit of claim 1 , further comprising a buffer operatively connected to said attenuator to lower an output capacitance of said attenuator.

7. The electrical circuit of claim 1 , wherein said attenuator is divided into sub-sections separated from one another by a buffer.

8. The electrical circuit of claim 1 , wherein each of said LNA signal line path and said attenuator signal line path further comprises:

an up-down counter; and

a fine gain step counter in a feedback configuration with said up-down counter.

9. A system configured for a communications device, said system comprising:

an antenna that receives a radio frequency (RF) signal;

a matching network that processes said RF signal;

a low noise amplifier (LNA) signal line path operatively connected to said matching network, said LNA signal line path comprising:

an LNA;

a first transconductor stage operatively connected to said LNA; and

a first signal mixer operatively connected to said first transconductor stage;

an attenuator signal line path operatively connected to said matching network, said attenuator signal line path comprising:

an attenuator;

a second transconductor stage operatively connected to said attenuator; and

a second signal mixer operatively connected to said second transconductor stage;

a RF power detector operatively connected to an output of each of said LNA and said attenuator, wherein said RF power detector varies a front end power gain of said system; and

logic circuitry operatively connected to said RF power detector, wherein said logic circuitry (i) selects transmission of a signal through only one of said LNA signal line path or said attenuator signal line path, and (ii) outputs the selected signal,

wherein each of said LNA signal line path and said attenuator signal line path comprises:

a comparator that creates a hysteresis boundary for preventing power gain limit cycles from occurring in each of said LNA signal line path and said attenuator signal line path;

an up-down counter operatively connected to said comparator; and

a fine gain step counter in a feedback configuration with said up-down counter.

10. The system of claim 9 , wherein said logic circuitry receives instructions from said RF power detector to switch between a LNA signal domain and an attenuator signal domain.

11. The system of claim 9 , wherein a power gain of said LNA is stepped such that signal glitches through the outputted selected signal are minimized.

12. The system of claim 9 , wherein said attenuator comprises a matching resistor in shunt with a signal through said attenuator signal line path.

13. The system of claim 9 , wherein said attenuator comprises a resistive divider configuration comprising transistor switches in shunt with a signal through said attenuator signal line path.

14. The system of claim 9 , further comprising a buffer operatively connected to said attenuator to lower an output capacitance of said attenuator.

15. The system of claim 9 , wherein said attenuator is divided into sub-sections separated from one another by a buffer.

16. A method for fine gain stepping and voltage bias control in an electrical circuit, said method comprising:

sending a first radio frequency (RF) signal through a low noise amplifier (LNA) signal line path, wherein said LNA signal line path comprises:

an LNA;

a first transconductor stage operatively connected to said LNA; and

a first signal mixer operatively connected to said first transconductor stage;

sending a second RF signal through an attenuator signal line path, wherein said attenuator signal line path comprises:

an attenuator;

a second transconductor stage operatively connected to said attenuator; and

a second signal mixer operatively connected to said second transconductor stage;

sending a signal output from each of said LNA and said attenuator to a RF power detector, wherein said RF power detector varies a front end power gain of said electrical circuit;

using logic circuitry to select transmission of a signal through only one of said LNA signal line path or said attenuator signal line path; and

outputting the selected signal.

17. The method of claim 16 , wherein said logic circuitry receives instructions from said RF power detector to switch between a LNA signal domain and an attenuator signal domain.

18. The method of claim 16 , wherein a power gain of said LNA is stepped such that signal glitches through the outputted selected signal are minimized.

19. The method of claim 16 , further comprising buffering an output signal from said attenuator in order to lower an output capacitance of said attenuator.

20. The method of claim 16 , further comprising dividing said attenuator into sub-sections separated from one another by a buffer.