METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION

1 . A computer implemented method for optimizing a register transfer level (RTL) description of an integrated circuit (IC) design, comprising:

assigning a unique definition for each variable in the RTL description;

for each variable having the unique definition, generating value range propagation;

performing one or more value-based optimization procedures on the RTL description, taking into account the value range propagation;

eliminating redundancy code in the RTL description;

optimizing algebraic and Boolean expressions in the RTL description; and

storing the resulting optimized RTL description in a memory.

2 . The method of claim 1 , wherein the RTL description includes a hardware description language (HDL) code.

3 . The method of claim 1 , wherein assigning the unique definition to each variable comprises generating a static single assignment (SSA) graph.

4 . The method of claim 3 , wherein generating the SSA graph comprises:

traversing a control data flow graph (CDFG);

replacing a variable of a left hand side (LHS) of each assignment in the RTL description with a new variable name; and

inserting a phi function, when encountering multiple definitions of a variable, reaching a use of a variable.

5 . The method of claim 4 , wherein the value range propagation detects the minimum and maximum values for each variable.

6 . The method of claim 5 , wherein generating the value range propagation comprises;

forward traversing the SSA graph to compute the value range propagation for the variable before an operation using the variable is encountered;

backward traversing the SSA graph to determine whether a variable of a LHS of an assignment constrains a right hand side (RHS) of the assignment; and

performing constant propagation to determine whether the variable has a constant value.

7 . The method of claim 1 , wherein the value-based optimization procedures comprise one or more of: bitwidth analysis, dead-code elimination, and loop structure optimization.

8 . The method of claim 1 , wherein eliminating the redundancy code comprises performing one or more of: value numbering to eliminate redundant computations, detection of common sub expressions (CSE), loop invariant code motion, and code hoisting.

9 . The method of claim 3 , wherein optimizing the algebraic and Boolean expressions comprises:

traversing the SSA graph;

applying a set of predefined rules on each expression in the SSA graph; and

replacing the expression with a respective simplified expression when one of the rules is satisfied.

10 . The method of claim 9 , wherein optimizing the Boolean expressions further comprises performing Shannon expansion optimization.

11 . The method of claim 1 , further comprising generating an optimized netlist, from the optimized RTL description, with a synthesis tool.

12 . The method of claim 1 , implemented in one of a computer aided design (CAD) system and a CAD program.

13 . A computer program product for enabling a computer system to perform operations for an integrated circuit (IC) design method, intended for optimizing a register transfer level (RTL) description of the IC design, the computer program product having computer instructions on a computer readable medium, the operations comprising:

assigning a unique definition for each variable in the RTL description;

for each variable having the unique definition, generating value range propagation;

performing one or more value-based optimization procedures on the RTL description, taking into account the value range propagation;

eliminating redundancy code in the RTL description; and

optimizing algebraic and Boolean expressions in the RTL description.

14 . The computer program product of claim 13 , wherein the RTL description includes a hardware description language (HDL) code.

15 . The computer program product of claim 13 , wherein assigning the unique definition to each variable comprises generating a static single assignment (SSA) graph.

16 . The computer program product of claim 15 , wherein generating the SSA graph comprises:

traversing a control data flow graph (CDFG);

replacing a variable of a left hand side (LHS) of each assignment in the RTL description with a new variable name; and

inserting a phi function when encountering multiple definitions of a variable, reaching a use of a variable.

17 . The computer program product of claim 16 , wherein the value range propagation detects the minimum and maximum values for each variable.

18 . The computer program product of claim 17 , wherein generating the value range propagation comprises;

forward traversing the SSA graph to compute the value range propagation for the variable before an operation using the variable is encountered;

backward traversing the SSA graph to determine whether a variable of a LHS of an assignment constrains a right hand side (RHS) of the assignment; and

performing constant propagation to determine whether the variable has a constant value.

19 . The computer program product of claim 18 , wherein the value-based optimization procedures comprise one or more of bitwidth analysis, dead-code elimination, and loop structure optimization.

20 . The computer program product of claim 13 , wherein eliminating the redundancy code comprises performing any of value numbering to eliminate redundant computations, detection of common sub expressions (CSE), loop invariant code motion, and code hoisting.

21 . The computer program product of claim 15 , wherein optimizing the algebraic and Boolean expressions comprises:

traversing the SSA graph;

applying a set of predefined rules on each expression in the SSA graph; and

replacing the expression with a respective simplified expression when one of the rules is satisfied.

22 . The computer program product of claim 21 , wherein optimizing the Boolean expressions further comprises performing Shannon expansion optimization.

23 . The computer program product of claim 13 , further comprising generating an optimized netlist, from the optimized RTL description, with a synthesis tool.

24 . The computer program product of claim 13 , implemented in one of a computer aided design (CAD) system and a CAD program.