IP Library › Assignment 022552/0639
Patent Assignment
Reel/Frame 022552/0639

Release of Security Interest

Recorded: 2009-04-17 Pages: 7
Assignor
Assignee
ATRENTA INC.
2077 GATEWAY DRIVE, SUITE 300, SAN JOSE, CALIFORNIA, 95110
Covered Properties (17)
Apparatus and Method for Handling of Multi-Level Circuit Design Data
Patent: 6,993,733 →
Application: 10/118,242 →
Publication: US 2003/0192023
Method for Detecting Bus Contention from Rtl Description
Patent: 7,277,840 →
Application: 10/172,996 →
Publication: US 2003/0233504
Method for Determining Fault Coverage from Rtl Description
Patent: 6,876,934 →
Application: 10/217,535 →
Publication: US 2004/0034495
Identification and Implementation of Clock Gating in the Design of Integrated Circuits
Patent: 7,076,748 →
Application: 10/631,755 →
Publication: US 2005/0028118
Method for Clock Synchronization Validation in Integrated Circuit Design
Patent: 7,073,146 →
Application: 10/695,803 →
Publication: US 2005/0097484
A Method, System, and Computer Program Product for Generating and Verifying Isolation Logic Modules in Design of Integrated Circuits
Patent: 7,349,835 →
Application: 10/711,493 →
Publication: US 2006/0064293
A Method, System, and Computer Program Product for Automatic Insertion and Correctness Verification of Level Shifters in Integrated Circuits with Multiple Voltage Domains
Patent: 7,152,216 →
Application: 10/711,971 →
Publication: US 2006/0085770
Pattern Recognition in an Integrated Circuit Design
Patent: 7,216,321 →
Application: 10/783,091 →
Publication: US 2005/0108675
A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design
Application: 10/906,571 →
Publication: US 2006/0190754
A Method of Optimization of Clock Gating in Integrated Circuit Designs
Patent: 7,546,559 →
Application: 11/419,624 →
Publication: US 2006/0248487
Bus Representation for Efficient Physical Synthesis of Integrated Circuit Designs
Patent: 7,451,427 →
Application: 11/423,919 →
Publication: US 2006/0282800
Method for Recognizing and Verifying Fifo Structures in Integrated Circuit Designs
Patent: 7,536,662 →
Application: 11/426,936 →
Publication: US 2008/0008021
Method for Generating Timing Exceptions
Application: 11/676,232 →
Publication: US 2008/0201671
Method for Accelerating the Generation of an Optimized Gate-Level Representation from a Rtl Representation
Application: 11/692,949 →
Publication: US 2008/0244472
Method for Modeling and Verifying Timing Exceptions
Patent: 7,650,581 →
Application: 11/749,090 →
Publication: US 2008/0288904
Method for Checking Constraints Equivalence of an Integrated Circuit Design
Patent: 7,882,483 →
Application: 11/755,764 →
Publication: US 2008/0301598
Method for Computing Power Savings and Determining the Preferred Clock Gating Circuit of an Integrated Circuit Design
Patent: 7,941,679 →
Application: 11/837,174 →
Publication: US 2009/0044033
Related Assignments (21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 1, 2003
From: KAPOOR, BHANU; CHURIWALA, SANJAY; BANERJEE, JOY
To: ATRENTA, INC.
Reel/Frame 014356/0397 →
Assignment of Assignor's Interest Oct 30, 2003
From: SARWARY, MOHAMED SHAKER; EZAZI, MOHAMMAD MOVAHED; MURPHY, BERNARD
To: ATRENTA INC.
Reel/Frame 014667/0380 →
Assignment of Assignor's Interest Sep 21, 2004
From: KAPOOR, BHANU; BAGCHI, DEBABRATA; CHURIWALA, SANJAY
To: ATRENTA, INC.
Reel/Frame 015155/0391 →
Assignment of Assignor's Interest Oct 15, 2004
From: KAPOOR, BHANU; BAGCHI, DEBABRATA
To: ATRENTA, INC.
Reel/Frame 015250/0734 →
Assignment of Assignor's Interest Feb 24, 2005
From: DARGELAS, ALAIN; MAL JAIN, PARAS; HARI, ASHISH; MURPHY, BERNARD
To: ATRENTA, INC.
Reel/Frame 015704/0503 →
Assignment of Assignor's Interest Mar 4, 2005
From: MURPHY, BERNARD; PRASOON, PRATYUSH KUMAR; BHATIA, MANISH
To: ATRENTA, INC.
Reel/Frame 016337/0671 →
Security Agreement Feb 2, 2006
From: ATRENTA, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 017105/0594 →
Assignment of Assignor's Interest Jul 10, 2006
From: KAPOOR, BHANU; BAGCHI, DEBABRATA; SHARMA, NITIN
To: ATRENTA, INC.
Reel/Frame 017904/0883 →
Security Agreement Aug 8, 2006
From: ATRENTA, INC.
To: COMERICA BANK
Reel/Frame 018073/0119 →
Assignment of Assignor's Interest Dec 14, 2006
From: SARWARY, SHAKER; YUAN, JUN; MURPHY, BERNARD; HARI, ASHISH
To: ATRENTA, INC.
Reel/Frame 018763/0716 →
Assignment of Assignor's Interest Feb 16, 2007
From: REJOUAN, HOUSSEINE; RAHIM, SOLAIMAN; MOVAHED-EZAZI, MOHAMMAD H.
To: ATRENTA, INC.
Reel/Frame 018901/0098 →
Assignment of Assignor's Interest Mar 29, 2007
From: NAYAK, ANSHUMAN; CHAKRABARTI, SAMANTAK; PAL, SATRAJIT; DEWAN, HITANSHU
To: ATRENTA, INC.
Reel/Frame 019081/0112 →
Assignment of Assignor's Interest May 16, 2007
From: RAHIM, SOLAIMAN; JAIN, MAYANK
To: ATRENTA, INC.
Reel/Frame 019302/0294 →
Assignment of Assignor's Interest Jul 23, 2007
From: GANGADHARAN, SRIDHAR; GOEL, MANISH; PRASOON, PRATYUSH K.; BHARECH, SURAJ
To: ATRENTA, INC.
Reel/Frame 019585/0076 →
Assignment of Assignor's Interest Aug 10, 2007
From: ALLEN, DAVID L.
To: ATRENTA, INC.
Reel/Frame 019680/0499 →
Security Agreement Jul 10, 2008
From: ATRENTA, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 021222/0668 →
Assignment of Assignor's Interest Oct 1, 2008
From: VARADARAJAN, RAVI
To: ATRENTA, INC.
Reel/Frame 021613/0168 →
Security Agreement Apr 15, 2009
From: ATRENTA INC.
To: SILICON VALLEY BANK
Reel/Frame 022542/0570 →
Release of Security Interest Apr 16, 2009
From: COMERICA BANK
To: ATRENTA, INC.
Reel/Frame 022552/0216 →
Release of Security Interest Sep 10, 2015
From: SILICON VALLEY BANK
To: ATRENTA INC.
Reel/Frame 036584/0644 →
Assignment of Assignor's Interest Sep 25, 2015
From: ATRENTA INC.
To: SYNOPSYS, INC.
Reel/Frame 036687/0290 →